82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
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/*
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* BCM2835 SPI Master Controller
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*
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* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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#include "hw/ssi/ssi.h"
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#include "qom/object.h"
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#include "qemu/fifo8.h"
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#define TYPE_BCM2835_SPI "bcm2835-spi"
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OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SPIState, BCM2835_SPI)
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/*
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* Though BCM2835 documentation says FIFOs have a capacity of 16,
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* FIFOs are actually 16 words in size or effectively 64 bytes when operating
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* in non DMA mode.
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*/
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#define FIFO_SIZE 64
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#define FIFO_SIZE_3_4 48
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#define RO_MASK 0x1f0000
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#define BCM2835_SPI_CS 0x00
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#define BCM2835_SPI_FIFO 0x04
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#define BCM2835_SPI_CLK 0x08
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#define BCM2835_SPI_DLEN 0x0c
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#define BCM2835_SPI_LTOH 0x10
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#define BCM2835_SPI_DC 0x14
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#define BCM2835_SPI_CS_RXF BIT(20)
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#define BCM2835_SPI_CS_RXR BIT(19)
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#define BCM2835_SPI_CS_TXD BIT(18)
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#define BCM2835_SPI_CS_RXD BIT(17)
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#define BCM2835_SPI_CS_DONE BIT(16)
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#define BCM2835_SPI_CS_LEN BIT(13)
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#define BCM2835_SPI_CS_REN BIT(12)
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#define BCM2835_SPI_CS_INTR BIT(10)
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#define BCM2835_SPI_CS_INTD BIT(9)
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#define BCM2835_SPI_CS_DMAEN BIT(8)
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#define BCM2835_SPI_CS_TA BIT(7)
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#define BCM2835_SPI_CLEAR_RX BIT(5)
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#define BCM2835_SPI_CLEAR_TX BIT(4)
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struct BCM2835SPIState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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SSIBus *bus;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t cs;
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uint32_t clk;
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uint32_t dlen;
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uint32_t ltoh;
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uint32_t dc;
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Fifo8 tx_fifo;
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Fifo8 rx_fifo;
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};
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