2015-09-24 02:29:37 +02:00
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/*
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* ARM Generic Interrupt Controller using KVM in-kernel support
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Pavel Fedin
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* Based on vGICv2 code by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2016-01-26 19:17:05 +01:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2015-09-24 02:29:37 +02:00
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/sysbus.h"
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2017-02-23 12:51:11 +01:00
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#include "qemu/error-report.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2015-09-24 02:29:37 +02:00
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#include "sysemu/kvm.h"
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2019-08-12 07:23:59 +02:00
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#include "sysemu/runstate.h"
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2015-09-24 02:29:37 +02:00
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#include "kvm_arm.h"
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2017-02-23 12:51:11 +01:00
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#include "gicv3_internal.h"
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2015-09-24 02:29:37 +02:00
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#include "vgic_common.h"
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2017-04-06 12:00:28 +02:00
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#include "migration/blocker.h"
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2015-09-24 02:29:37 +02:00
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#ifdef DEBUG_GICV3_KVM
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3"
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#define KVM_ARM_GICV3(obj) \
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OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3)
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#define KVM_ARM_GICV3_CLASS(klass) \
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OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3)
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#define KVM_ARM_GICV3_GET_CLASS(obj) \
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OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
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2017-02-23 12:51:11 +01:00
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#define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
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(ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
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ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
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ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
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ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
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ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
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#define ICC_PMR_EL1 \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
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#define ICC_BPR0_EL1 \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
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#define ICC_AP0R_EL1(n) \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
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#define ICC_AP1R_EL1(n) \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
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#define ICC_BPR1_EL1 \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
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#define ICC_CTLR_EL1 \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
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#define ICC_SRE_EL1 \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
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#define ICC_IGRPEN0_EL1 \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
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#define ICC_IGRPEN1_EL1 \
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KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
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2015-09-24 02:29:37 +02:00
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typedef struct KVMARMGICv3Class {
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ARMGICv3CommonClass parent_class;
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DeviceRealize parent_realize;
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void (*parent_reset)(DeviceState *dev);
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} KVMARMGICv3Class;
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static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
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{
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GICv3State *s = (GICv3State *)opaque;
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kvm_arm_gic_set_irq(s->num_irq, irq, level);
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}
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2017-02-23 12:51:11 +01:00
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#define KVM_VGIC_ATTR(reg, typer) \
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((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
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static inline void kvm_gicd_access(GICv3State *s, int offset,
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uint32_t *val, bool write)
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{
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
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KVM_VGIC_ATTR(offset, 0),
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2017-06-13 15:57:00 +02:00
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val, write, &error_abort);
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2017-02-23 12:51:11 +01:00
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}
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static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
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uint32_t *val, bool write)
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{
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
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KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
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2017-06-13 15:57:00 +02:00
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val, write, &error_abort);
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2017-02-23 12:51:11 +01:00
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}
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static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
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uint64_t *val, bool write)
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{
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
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KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
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2017-06-13 15:57:00 +02:00
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val, write, &error_abort);
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2017-02-23 12:51:11 +01:00
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}
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static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
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uint32_t *val, bool write)
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{
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
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KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
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(VGIC_LEVEL_INFO_LINE_LEVEL <<
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KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
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2017-06-13 15:57:00 +02:00
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val, write, &error_abort);
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2017-02-23 12:51:11 +01:00
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}
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/* Loop through each distributor IRQ related register; since bits
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* corresponding to SPIs and PPIs are RAZ/WI when affinity routing
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* is enabled, we skip those.
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*/
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#define for_each_dist_irq_reg(_irq, _max, _field_width) \
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for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
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static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
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{
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uint32_t reg, *field;
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int irq;
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2018-06-15 15:57:13 +02:00
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/* For the KVM GICv3, affinity routing is always enabled, and the first 8
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* GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding
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* functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to
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* sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and
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* offset.
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*/
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field = (uint32_t *)(bmp + GIC_INTERNAL);
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offset += (GIC_INTERNAL * 8) / 8;
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2017-02-23 12:51:11 +01:00
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for_each_dist_irq_reg(irq, s->num_irq, 8) {
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kvm_gicd_access(s, offset, ®, false);
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*field = reg;
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offset += 4;
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field++;
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}
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}
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static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
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{
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uint32_t reg, *field;
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int irq;
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2018-06-15 15:57:13 +02:00
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/* For the KVM GICv3, affinity routing is always enabled, and the first 8
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* GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding
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* functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to
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* sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and
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* offset.
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*/
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field = (uint32_t *)(bmp + GIC_INTERNAL);
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offset += (GIC_INTERNAL * 8) / 8;
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2017-02-23 12:51:11 +01:00
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for_each_dist_irq_reg(irq, s->num_irq, 8) {
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reg = *field;
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kvm_gicd_access(s, offset, ®, true);
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offset += 4;
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field++;
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}
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}
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static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
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uint32_t *bmp)
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{
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uint32_t reg;
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int irq;
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2018-06-08 14:15:32 +02:00
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/* For the KVM GICv3, affinity routing is always enabled, and the first 2
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* GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
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* functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
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* them. So it should increase the offset to skip GIC_INTERNAL irqs.
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* This matches the for_each_dist_irq_reg() macro which also skips the
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* first GIC_INTERNAL irqs.
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*/
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offset += (GIC_INTERNAL * 2) / 8;
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2017-02-23 12:51:11 +01:00
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for_each_dist_irq_reg(irq, s->num_irq, 2) {
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kvm_gicd_access(s, offset, ®, false);
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reg = half_unshuffle32(reg >> 1);
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if (irq % 32 != 0) {
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reg = (reg << 16);
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}
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*gic_bmp_ptr32(bmp, irq) |= reg;
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offset += 4;
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}
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}
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static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
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uint32_t *bmp)
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{
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uint32_t reg;
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int irq;
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2018-06-08 14:15:32 +02:00
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/* For the KVM GICv3, affinity routing is always enabled, and the first 2
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* GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
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* functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
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* them. So it should increase the offset to skip GIC_INTERNAL irqs.
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* This matches the for_each_dist_irq_reg() macro which also skips the
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* first GIC_INTERNAL irqs.
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*/
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offset += (GIC_INTERNAL * 2) / 8;
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2017-02-23 12:51:11 +01:00
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for_each_dist_irq_reg(irq, s->num_irq, 2) {
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reg = *gic_bmp_ptr32(bmp, irq);
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if (irq % 32 != 0) {
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reg = (reg & 0xffff0000) >> 16;
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} else {
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reg = reg & 0xffff;
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}
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reg = half_shuffle32(reg) << 1;
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kvm_gicd_access(s, offset, ®, true);
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offset += 4;
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}
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}
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static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp)
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{
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uint32_t reg;
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int irq;
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for_each_dist_irq_reg(irq, s->num_irq, 1) {
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kvm_gic_line_level_access(s, irq, 0, ®, false);
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*gic_bmp_ptr32(bmp, irq) = reg;
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}
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}
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static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp)
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{
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uint32_t reg;
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int irq;
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for_each_dist_irq_reg(irq, s->num_irq, 1) {
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reg = *gic_bmp_ptr32(bmp, irq);
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kvm_gic_line_level_access(s, irq, 0, ®, true);
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}
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}
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/* Read a bitmap register group from the kernel VGIC. */
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static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
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{
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uint32_t reg;
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int irq;
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|
2018-06-08 14:15:32 +02:00
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/* For the KVM GICv3, affinity routing is always enabled, and the
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* GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
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* GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
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* functionality is replaced by the GICR registers. It doesn't need to sync
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* them. So it should increase the offset to skip GIC_INTERNAL irqs.
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* This matches the for_each_dist_irq_reg() macro which also skips the
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* first GIC_INTERNAL irqs.
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*/
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offset += (GIC_INTERNAL * 1) / 8;
|
2017-02-23 12:51:11 +01:00
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for_each_dist_irq_reg(irq, s->num_irq, 1) {
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kvm_gicd_access(s, offset, ®, false);
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*gic_bmp_ptr32(bmp, irq) = reg;
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offset += 4;
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}
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}
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static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
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uint32_t clroffset, uint32_t *bmp)
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{
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uint32_t reg;
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int irq;
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|
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|
2018-06-08 14:15:32 +02:00
|
|
|
/* For the KVM GICv3, affinity routing is always enabled, and the
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|
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* GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
|
|
|
|
* GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
|
|
|
|
* functionality is replaced by the GICR registers. It doesn't need to sync
|
|
|
|
* them. So it should increase the offset and clroffset to skip GIC_INTERNAL
|
|
|
|
* irqs. This matches the for_each_dist_irq_reg() macro which also skips the
|
|
|
|
* first GIC_INTERNAL irqs.
|
|
|
|
*/
|
|
|
|
offset += (GIC_INTERNAL * 1) / 8;
|
|
|
|
if (clroffset != 0) {
|
|
|
|
clroffset += (GIC_INTERNAL * 1) / 8;
|
|
|
|
}
|
|
|
|
|
2017-02-23 12:51:11 +01:00
|
|
|
for_each_dist_irq_reg(irq, s->num_irq, 1) {
|
|
|
|
/* If this bitmap is a set/clear register pair, first write to the
|
|
|
|
* clear-reg to clear all bits before using the set-reg to write
|
|
|
|
* the 1 bits.
|
|
|
|
*/
|
|
|
|
if (clroffset != 0) {
|
|
|
|
reg = 0;
|
|
|
|
kvm_gicd_access(s, clroffset, ®, true);
|
2018-05-31 15:50:51 +02:00
|
|
|
clroffset += 4;
|
2017-02-23 12:51:11 +01:00
|
|
|
}
|
|
|
|
reg = *gic_bmp_ptr32(bmp, irq);
|
|
|
|
kvm_gicd_access(s, offset, ®, true);
|
|
|
|
offset += 4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void kvm_arm_gicv3_check(GICv3State *s)
|
|
|
|
{
|
|
|
|
uint32_t reg;
|
|
|
|
uint32_t num_irq;
|
|
|
|
|
|
|
|
/* Sanity checking s->num_irq */
|
|
|
|
kvm_gicd_access(s, GICD_TYPER, ®, false);
|
|
|
|
num_irq = ((reg & 0x1f) + 1) * 32;
|
|
|
|
|
|
|
|
if (num_irq < s->num_irq) {
|
|
|
|
error_report("Model requests %u IRQs, but kernel supports max %u",
|
|
|
|
s->num_irq, num_irq);
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-24 02:29:37 +02:00
|
|
|
static void kvm_arm_gicv3_put(GICv3State *s)
|
|
|
|
{
|
2017-02-23 12:51:11 +01:00
|
|
|
uint32_t regl, regh, reg;
|
|
|
|
uint64_t reg64, redist_typer;
|
|
|
|
int ncpu, i;
|
|
|
|
|
|
|
|
kvm_arm_gicv3_check(s);
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_TYPER, 0, ®l, false);
|
|
|
|
kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false);
|
|
|
|
redist_typer = ((uint64_t)regh << 32) | regl;
|
|
|
|
|
|
|
|
reg = s->gicd_ctlr;
|
|
|
|
kvm_gicd_access(s, GICD_CTLR, ®, true);
|
|
|
|
|
|
|
|
if (redist_typer & GICR_TYPER_PLPIS) {
|
|
|
|
/* Set base addresses before LPIs are enabled by GICR_CTLR write */
|
|
|
|
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
|
|
|
|
GICv3CPUState *c = &s->cpu[ncpu];
|
|
|
|
|
|
|
|
reg64 = c->gicr_propbaser;
|
|
|
|
regl = (uint32_t)reg64;
|
|
|
|
kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true);
|
|
|
|
regh = (uint32_t)(reg64 >> 32);
|
|
|
|
kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true);
|
|
|
|
|
|
|
|
reg64 = c->gicr_pendbaser;
|
2017-09-04 16:21:56 +02:00
|
|
|
if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
|
2017-02-23 12:51:11 +01:00
|
|
|
/* Setting PTZ is advised if LPIs are disabled, to reduce
|
|
|
|
* GIC initialization time.
|
|
|
|
*/
|
|
|
|
reg64 |= GICR_PENDBASER_PTZ;
|
|
|
|
}
|
|
|
|
regl = (uint32_t)reg64;
|
|
|
|
kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true);
|
|
|
|
regh = (uint32_t)(reg64 >> 32);
|
|
|
|
kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Redistributor state (one per CPU) */
|
|
|
|
|
|
|
|
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
|
|
|
|
GICv3CPUState *c = &s->cpu[ncpu];
|
|
|
|
|
|
|
|
reg = c->gicr_ctlr;
|
|
|
|
kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true);
|
|
|
|
|
|
|
|
reg = c->gicr_statusr[GICV3_NS];
|
|
|
|
kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true);
|
|
|
|
|
|
|
|
reg = c->gicr_waker;
|
|
|
|
kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true);
|
|
|
|
|
|
|
|
reg = c->gicr_igroupr0;
|
|
|
|
kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true);
|
|
|
|
|
|
|
|
reg = ~0;
|
|
|
|
kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true);
|
|
|
|
reg = c->gicr_ienabler0;
|
|
|
|
kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true);
|
|
|
|
|
|
|
|
/* Restore config before pending so we treat level/edge correctly */
|
|
|
|
reg = half_shuffle32(c->edge_trigger >> 16) << 1;
|
|
|
|
kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true);
|
|
|
|
|
|
|
|
reg = c->level;
|
|
|
|
kvm_gic_line_level_access(s, 0, ncpu, ®, true);
|
|
|
|
|
|
|
|
reg = ~0;
|
|
|
|
kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true);
|
|
|
|
reg = c->gicr_ipendr0;
|
|
|
|
kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true);
|
|
|
|
|
|
|
|
reg = ~0;
|
|
|
|
kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true);
|
|
|
|
reg = c->gicr_iactiver0;
|
|
|
|
kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true);
|
|
|
|
|
|
|
|
for (i = 0; i < GIC_INTERNAL; i += 4) {
|
|
|
|
reg = c->gicr_ipriorityr[i] |
|
|
|
|
(c->gicr_ipriorityr[i + 1] << 8) |
|
|
|
|
(c->gicr_ipriorityr[i + 2] << 16) |
|
|
|
|
(c->gicr_ipriorityr[i + 3] << 24);
|
|
|
|
kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Distributor state (shared between all CPUs */
|
|
|
|
reg = s->gicd_statusr[GICV3_NS];
|
|
|
|
kvm_gicd_access(s, GICD_STATUSR, ®, true);
|
|
|
|
|
|
|
|
/* s->enable bitmap -> GICD_ISENABLERn */
|
|
|
|
kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
|
|
|
|
|
|
|
|
/* s->group bitmap -> GICD_IGROUPRn */
|
|
|
|
kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
|
|
|
|
|
|
|
|
/* Restore targets before pending to ensure the pending state is set on
|
|
|
|
* the appropriate CPU interfaces in the kernel
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* s->gicd_irouter[irq] -> GICD_IROUTERn
|
|
|
|
* We can't use kvm_dist_put() here because the registers are 64-bit
|
|
|
|
*/
|
|
|
|
for (i = GIC_INTERNAL; i < s->num_irq; i++) {
|
|
|
|
uint32_t offset;
|
|
|
|
|
|
|
|
offset = GICD_IROUTER + (sizeof(uint32_t) * i);
|
|
|
|
reg = (uint32_t)s->gicd_irouter[i];
|
|
|
|
kvm_gicd_access(s, offset, ®, true);
|
|
|
|
|
|
|
|
offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
|
|
|
|
reg = (uint32_t)(s->gicd_irouter[i] >> 32);
|
|
|
|
kvm_gicd_access(s, offset, ®, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* s->trigger bitmap -> GICD_ICFGRn
|
|
|
|
* (restore configuration registers before pending IRQs so we treat
|
|
|
|
* level/edge correctly)
|
|
|
|
*/
|
|
|
|
kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
|
|
|
|
|
|
|
|
/* s->level bitmap -> line_level */
|
|
|
|
kvm_gic_put_line_level_bmp(s, s->level);
|
|
|
|
|
|
|
|
/* s->pending bitmap -> GICD_ISPENDRn */
|
|
|
|
kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
|
|
|
|
|
|
|
|
/* s->active bitmap -> GICD_ISACTIVERn */
|
|
|
|
kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
|
|
|
|
|
|
|
|
/* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
|
|
|
|
kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
|
|
|
|
|
|
|
|
/* CPU Interface state (one per CPU) */
|
|
|
|
|
|
|
|
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
|
|
|
|
GICv3CPUState *c = &s->cpu[ncpu];
|
|
|
|
int num_pri_bits;
|
|
|
|
|
|
|
|
kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
|
|
|
|
kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
|
|
|
|
&c->icc_ctlr_el1[GICV3_NS], true);
|
|
|
|
kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
|
|
|
|
&c->icc_igrpen[GICV3_G0], true);
|
|
|
|
kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
|
|
|
|
&c->icc_igrpen[GICV3_G1NS], true);
|
|
|
|
kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
|
|
|
|
kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
|
|
|
|
kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
|
|
|
|
|
|
|
|
num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
|
|
|
|
ICC_CTLR_EL1_PRIBITS_MASK) >>
|
|
|
|
ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
|
|
|
|
|
|
|
|
switch (num_pri_bits) {
|
|
|
|
case 7:
|
|
|
|
reg64 = c->icc_apr[GICV3_G0][3];
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true);
|
|
|
|
reg64 = c->icc_apr[GICV3_G0][2];
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true);
|
|
|
|
case 6:
|
|
|
|
reg64 = c->icc_apr[GICV3_G0][1];
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true);
|
|
|
|
default:
|
|
|
|
reg64 = c->icc_apr[GICV3_G0][0];
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (num_pri_bits) {
|
|
|
|
case 7:
|
|
|
|
reg64 = c->icc_apr[GICV3_G1NS][3];
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true);
|
|
|
|
reg64 = c->icc_apr[GICV3_G1NS][2];
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true);
|
|
|
|
case 6:
|
|
|
|
reg64 = c->icc_apr[GICV3_G1NS][1];
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true);
|
|
|
|
default:
|
|
|
|
reg64 = c->icc_apr[GICV3_G1NS][0];
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true);
|
|
|
|
}
|
|
|
|
}
|
2015-09-24 02:29:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void kvm_arm_gicv3_get(GICv3State *s)
|
|
|
|
{
|
2017-02-23 12:51:11 +01:00
|
|
|
uint32_t regl, regh, reg;
|
|
|
|
uint64_t reg64, redist_typer;
|
|
|
|
int ncpu, i;
|
|
|
|
|
|
|
|
kvm_arm_gicv3_check(s);
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_TYPER, 0, ®l, false);
|
|
|
|
kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false);
|
|
|
|
redist_typer = ((uint64_t)regh << 32) | regl;
|
|
|
|
|
|
|
|
kvm_gicd_access(s, GICD_CTLR, ®, false);
|
|
|
|
s->gicd_ctlr = reg;
|
|
|
|
|
|
|
|
/* Redistributor state (one per CPU) */
|
|
|
|
|
|
|
|
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
|
|
|
|
GICv3CPUState *c = &s->cpu[ncpu];
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false);
|
|
|
|
c->gicr_ctlr = reg;
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false);
|
|
|
|
c->gicr_statusr[GICV3_NS] = reg;
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false);
|
|
|
|
c->gicr_waker = reg;
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false);
|
|
|
|
c->gicr_igroupr0 = reg;
|
|
|
|
kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false);
|
|
|
|
c->gicr_ienabler0 = reg;
|
|
|
|
kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false);
|
|
|
|
c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
|
|
|
|
kvm_gic_line_level_access(s, 0, ncpu, ®, false);
|
|
|
|
c->level = reg;
|
|
|
|
kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false);
|
|
|
|
c->gicr_ipendr0 = reg;
|
|
|
|
kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false);
|
|
|
|
c->gicr_iactiver0 = reg;
|
|
|
|
|
|
|
|
for (i = 0; i < GIC_INTERNAL; i += 4) {
|
|
|
|
kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false);
|
|
|
|
c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
|
|
|
|
c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
|
|
|
|
c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
|
|
|
|
c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (redist_typer & GICR_TYPER_PLPIS) {
|
|
|
|
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
|
|
|
|
GICv3CPUState *c = &s->cpu[ncpu];
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false);
|
|
|
|
kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false);
|
|
|
|
c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
|
|
|
|
|
|
|
|
kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false);
|
|
|
|
kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false);
|
|
|
|
c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Distributor state (shared between all CPUs */
|
|
|
|
|
|
|
|
kvm_gicd_access(s, GICD_STATUSR, ®, false);
|
|
|
|
s->gicd_statusr[GICV3_NS] = reg;
|
|
|
|
|
|
|
|
/* GICD_IGROUPRn -> s->group bitmap */
|
|
|
|
kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
|
|
|
|
|
|
|
|
/* GICD_ISENABLERn -> s->enabled bitmap */
|
|
|
|
kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
|
|
|
|
|
|
|
|
/* Line level of irq */
|
|
|
|
kvm_gic_get_line_level_bmp(s, s->level);
|
|
|
|
/* GICD_ISPENDRn -> s->pending bitmap */
|
|
|
|
kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
|
|
|
|
|
|
|
|
/* GICD_ISACTIVERn -> s->active bitmap */
|
|
|
|
kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
|
|
|
|
|
|
|
|
/* GICD_ICFGRn -> s->trigger bitmap */
|
|
|
|
kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
|
|
|
|
|
|
|
|
/* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
|
|
|
|
kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
|
|
|
|
|
|
|
|
/* GICD_IROUTERn -> s->gicd_irouter[irq] */
|
|
|
|
for (i = GIC_INTERNAL; i < s->num_irq; i++) {
|
|
|
|
uint32_t offset;
|
|
|
|
|
|
|
|
offset = GICD_IROUTER + (sizeof(uint32_t) * i);
|
|
|
|
kvm_gicd_access(s, offset, ®l, false);
|
|
|
|
offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
|
|
|
|
kvm_gicd_access(s, offset, ®h, false);
|
|
|
|
s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************
|
|
|
|
* CPU Interface(s) State
|
|
|
|
*/
|
|
|
|
|
|
|
|
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
|
|
|
|
GICv3CPUState *c = &s->cpu[ncpu];
|
|
|
|
int num_pri_bits;
|
|
|
|
|
|
|
|
kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
|
|
|
|
kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
|
|
|
|
&c->icc_ctlr_el1[GICV3_NS], false);
|
|
|
|
kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
|
|
|
|
&c->icc_igrpen[GICV3_G0], false);
|
|
|
|
kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
|
|
|
|
&c->icc_igrpen[GICV3_G1NS], false);
|
|
|
|
kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
|
|
|
|
kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
|
|
|
|
kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
|
|
|
|
num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
|
|
|
|
ICC_CTLR_EL1_PRIBITS_MASK) >>
|
|
|
|
ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
|
|
|
|
|
|
|
|
switch (num_pri_bits) {
|
|
|
|
case 7:
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G0][3] = reg64;
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G0][2] = reg64;
|
|
|
|
case 6:
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G0][1] = reg64;
|
|
|
|
default:
|
|
|
|
kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G0][0] = reg64;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (num_pri_bits) {
|
|
|
|
case 7:
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G1NS][3] = reg64;
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G1NS][2] = reg64;
|
|
|
|
case 6:
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G1NS][1] = reg64;
|
|
|
|
default:
|
|
|
|
kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false);
|
|
|
|
c->icc_apr[GICV3_G1NS][0] = reg64;
|
|
|
|
}
|
|
|
|
}
|
2015-09-24 02:29:37 +02:00
|
|
|
}
|
|
|
|
|
2017-02-23 12:51:13 +01:00
|
|
|
static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu;
|
|
|
|
GICv3State *s;
|
|
|
|
GICv3CPUState *c;
|
|
|
|
|
|
|
|
c = (GICv3CPUState *)env->gicv3state;
|
|
|
|
s = c->gic;
|
|
|
|
cpu = ARM_CPU(c->cpu);
|
|
|
|
|
|
|
|
c->icc_pmr_el1 = 0;
|
|
|
|
c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
|
|
|
|
c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
|
|
|
|
c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
|
|
|
|
|
|
|
|
c->icc_sre_el1 = 0x7;
|
|
|
|
memset(c->icc_apr, 0, sizeof(c->icc_apr));
|
|
|
|
memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
|
2017-03-28 19:20:40 +02:00
|
|
|
|
|
|
|
if (s->migration_blocker) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize to actual HW supported configuration */
|
|
|
|
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
|
|
|
|
KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
|
2017-06-13 15:57:00 +02:00
|
|
|
&c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
|
2017-03-28 19:20:40 +02:00
|
|
|
|
|
|
|
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
|
2017-02-23 12:51:13 +01:00
|
|
|
}
|
|
|
|
|
2015-09-24 02:29:37 +02:00
|
|
|
static void kvm_arm_gicv3_reset(DeviceState *dev)
|
|
|
|
{
|
|
|
|
GICv3State *s = ARM_GICV3_COMMON(dev);
|
|
|
|
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
|
|
|
|
|
|
|
|
DPRINTF("Reset\n");
|
|
|
|
|
|
|
|
kgc->parent_reset(dev);
|
2017-02-23 12:51:11 +01:00
|
|
|
|
|
|
|
if (s->migration_blocker) {
|
|
|
|
DPRINTF("Cannot put kernel gic state, no kernel interface\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-09-24 02:29:37 +02:00
|
|
|
kvm_arm_gicv3_put(s);
|
|
|
|
}
|
|
|
|
|
2017-02-23 12:51:13 +01:00
|
|
|
/*
|
|
|
|
* CPU interface registers of GIC needs to be reset on CPU reset.
|
|
|
|
* For the calling arm_gicv3_icc_reset() on CPU reset, we register
|
|
|
|
* below ARMCPRegInfo. As we reset the whole cpu interface under single
|
|
|
|
* register reset, we define only one register of CPU interface instead
|
|
|
|
* of defining all the registers.
|
|
|
|
*/
|
|
|
|
static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
|
|
|
|
{ .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
|
|
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
|
|
|
|
/*
|
|
|
|
* If ARM_CP_NOP is used, resetfn is not called,
|
|
|
|
* So ARM_CP_NO_RAW is appropriate type.
|
|
|
|
*/
|
|
|
|
.type = ARM_CP_NO_RAW,
|
|
|
|
.access = PL1_RW,
|
|
|
|
.readfn = arm_cp_read_zero,
|
|
|
|
.writefn = arm_cp_write_ignore,
|
|
|
|
/*
|
|
|
|
* We hang the whole cpu interface reset routine off here
|
|
|
|
* rather than parcelling it out into one little function
|
|
|
|
* per register
|
|
|
|
*/
|
|
|
|
.resetfn = arm_gicv3_icc_reset,
|
|
|
|
},
|
|
|
|
REGINFO_SENTINEL
|
|
|
|
};
|
|
|
|
|
2017-06-13 15:57:00 +02:00
|
|
|
/**
|
|
|
|
* vm_change_state_handler - VM change state callback aiming at flushing
|
|
|
|
* RDIST pending tables into guest RAM
|
|
|
|
*
|
|
|
|
* The tables get flushed to guest RAM whenever the VM gets stopped.
|
|
|
|
*/
|
|
|
|
static void vm_change_state_handler(void *opaque, int running,
|
|
|
|
RunState state)
|
|
|
|
{
|
|
|
|
GICv3State *s = (GICv3State *)opaque;
|
|
|
|
Error *err = NULL;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (running) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
|
|
|
|
KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES,
|
|
|
|
NULL, true, &err);
|
|
|
|
if (err) {
|
|
|
|
error_report_err(err);
|
|
|
|
}
|
|
|
|
if (ret < 0 && ret != -EFAULT) {
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2015-09-24 02:29:37 +02:00
|
|
|
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
GICv3State *s = KVM_ARM_GICV3(dev);
|
|
|
|
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
|
2018-06-22 14:28:36 +02:00
|
|
|
bool multiple_redist_region_allowed;
|
2015-09-24 02:29:37 +02:00
|
|
|
Error *local_err = NULL;
|
2016-10-04 14:28:08 +02:00
|
|
|
int i;
|
2015-09-24 02:29:37 +02:00
|
|
|
|
|
|
|
DPRINTF("kvm_arm_gicv3_realize\n");
|
|
|
|
|
|
|
|
kgc->parent_realize(dev, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->security_extn) {
|
|
|
|
error_setg(errp, "the in-kernel VGICv3 does not implement the "
|
|
|
|
"security extensions");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-06-22 14:28:36 +02:00
|
|
|
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
2015-09-24 02:29:37 +02:00
|
|
|
|
2017-02-23 12:51:13 +01:00
|
|
|
for (i = 0; i < s->num_cpu; i++) {
|
|
|
|
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
|
|
|
|
|
|
|
|
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
|
|
|
|
}
|
|
|
|
|
2015-09-24 02:29:37 +02:00
|
|
|
/* Try to create the device via the device control API */
|
|
|
|
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
|
|
|
|
if (s->dev_fd < 0) {
|
|
|
|
error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-06-22 14:28:36 +02:00
|
|
|
multiple_redist_region_allowed =
|
|
|
|
kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
|
|
|
|
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION);
|
|
|
|
|
|
|
|
if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) {
|
|
|
|
error_setg(errp, "Multiple VGICv3 redistributor regions are not "
|
|
|
|
"supported by this host kernel");
|
|
|
|
error_append_hint(errp, "A maximum of %d VCPUs can be used",
|
|
|
|
s->redist_region_count[0]);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-09-24 02:29:37 +02:00
|
|
|
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
|
2017-06-13 15:57:00 +02:00
|
|
|
0, &s->num_irq, true, &error_abort);
|
2015-09-24 02:29:37 +02:00
|
|
|
|
|
|
|
/* Tell the kernel to complete VGIC initialization now */
|
|
|
|
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
|
2017-06-13 15:57:00 +02:00
|
|
|
KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
|
2015-09-24 02:29:37 +02:00
|
|
|
|
|
|
|
kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
|
2018-06-22 14:28:35 +02:00
|
|
|
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
|
2018-06-22 14:28:36 +02:00
|
|
|
|
|
|
|
if (!multiple_redist_region_allowed) {
|
|
|
|
kvm_arm_register_device(&s->iomem_redist[0], -1,
|
|
|
|
KVM_DEV_ARM_VGIC_GRP_ADDR,
|
|
|
|
KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
|
|
|
|
} else {
|
|
|
|
/* we register regions in reverse order as "devices" are inserted at
|
|
|
|
* the head of a QSLIST and the list is then popped from the head
|
|
|
|
* onwards by kvm_arm_machine_init_done()
|
|
|
|
*/
|
|
|
|
for (i = s->nb_redist_regions - 1; i >= 0; i--) {
|
|
|
|
/* Address mask made of the rdist region index and count */
|
|
|
|
uint64_t addr_ormask =
|
|
|
|
i | ((uint64_t)s->redist_region_count[i] << 52);
|
|
|
|
|
|
|
|
kvm_arm_register_device(&s->iomem_redist[i], -1,
|
|
|
|
KVM_DEV_ARM_VGIC_GRP_ADDR,
|
|
|
|
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,
|
|
|
|
s->dev_fd, addr_ormask);
|
|
|
|
}
|
|
|
|
}
|
2016-06-17 16:23:46 +02:00
|
|
|
|
2016-10-04 14:28:08 +02:00
|
|
|
if (kvm_has_gsi_routing()) {
|
|
|
|
/* set up irq routing */
|
|
|
|
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
|
|
|
|
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
kvm_gsi_routing_allowed = true;
|
|
|
|
|
|
|
|
kvm_irqchip_commit_routes(kvm_state);
|
|
|
|
}
|
2017-02-23 12:51:11 +01:00
|
|
|
|
|
|
|
if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
|
|
|
|
GICD_CTLR)) {
|
|
|
|
error_setg(&s->migration_blocker, "This operating system kernel does "
|
|
|
|
"not support vGICv3 migration");
|
|
|
|
migrate_add_blocker(s->migration_blocker, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
error_free(s->migration_blocker);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2017-06-13 15:57:00 +02:00
|
|
|
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
|
|
|
|
KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) {
|
|
|
|
qemu_add_vm_change_state_handler(vm_change_state_handler, s);
|
|
|
|
}
|
2015-09-24 02:29:37 +02:00
|
|
|
}
|
|
|
|
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static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
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KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass);
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agcc->pre_save = kvm_arm_gicv3_get;
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agcc->post_load = kvm_arm_gicv3_put;
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2018-01-14 03:04:12 +01:00
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device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
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&kgc->parent_realize);
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device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
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2015-09-24 02:29:37 +02:00
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}
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static const TypeInfo kvm_arm_gicv3_info = {
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.name = TYPE_KVM_ARM_GICV3,
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.parent = TYPE_ARM_GICV3_COMMON,
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.instance_size = sizeof(GICv3State),
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.class_init = kvm_arm_gicv3_class_init,
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.class_size = sizeof(KVMARMGICv3Class),
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};
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static void kvm_arm_gicv3_register_types(void)
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{
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type_register_static(&kvm_arm_gicv3_info);
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}
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type_init(kvm_arm_gicv3_register_types)
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