320 lines
10 KiB
C
320 lines
10 KiB
C
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/*
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* QTests for Nuvoton NPCM7xx Timer Watchdog Modules.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "libqos/libqtest.h"
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#include "qapi/qmp/qdict.h"
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#define WTCR_OFFSET 0x1c
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#define REF_HZ (25000000)
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/* WTCR bit fields */
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#define WTCLK(rv) ((rv) << 10)
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#define WTE BIT(7)
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#define WTIE BIT(6)
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#define WTIS(rv) ((rv) << 4)
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#define WTIF BIT(3)
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#define WTRF BIT(2)
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#define WTRE BIT(1)
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#define WTR BIT(0)
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typedef struct Watchdog {
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int irq;
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uint64_t base_addr;
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} Watchdog;
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static const Watchdog watchdog_list[] = {
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{
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.irq = 47,
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.base_addr = 0xf0008000
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},
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{
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.irq = 48,
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.base_addr = 0xf0009000
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},
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{
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.irq = 49,
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.base_addr = 0xf000a000
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}
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};
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static int watchdog_index(const Watchdog *wd)
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{
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ptrdiff_t diff = wd - watchdog_list;
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g_assert(diff >= 0 && diff < ARRAY_SIZE(watchdog_list));
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return diff;
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}
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static uint32_t watchdog_read_wtcr(QTestState *qts, const Watchdog *wd)
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{
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return qtest_readl(qts, wd->base_addr + WTCR_OFFSET);
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}
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static void watchdog_write_wtcr(QTestState *qts, const Watchdog *wd,
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uint32_t value)
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{
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qtest_writel(qts, wd->base_addr + WTCR_OFFSET, value);
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}
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static uint32_t watchdog_prescaler(QTestState *qts, const Watchdog *wd)
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{
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switch (extract32(watchdog_read_wtcr(qts, wd), 10, 2)) {
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case 0:
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return 1;
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case 1:
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return 256;
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case 2:
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return 2048;
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case 3:
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return 65536;
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default:
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g_assert_not_reached();
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}
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}
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static QDict *get_watchdog_action(QTestState *qts)
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{
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QDict *ev = qtest_qmp_eventwait_ref(qts, "WATCHDOG");
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QDict *data;
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data = qdict_get_qdict(ev, "data");
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qobject_ref(data);
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qobject_unref(ev);
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return data;
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}
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#define RESET_CYCLES 1024
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static uint32_t watchdog_interrupt_cycles(QTestState *qts, const Watchdog *wd)
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{
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uint32_t wtis = extract32(watchdog_read_wtcr(qts, wd), 4, 2);
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return 1 << (14 + 2 * wtis);
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}
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static int64_t watchdog_calculate_steps(uint32_t count, uint32_t prescale)
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{
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return (NANOSECONDS_PER_SECOND / REF_HZ) * count * prescale;
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}
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static int64_t watchdog_interrupt_steps(QTestState *qts, const Watchdog *wd)
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{
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return watchdog_calculate_steps(watchdog_interrupt_cycles(qts, wd),
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watchdog_prescaler(qts, wd));
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}
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/* Check wtcr can be reset to default value */
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static void test_init(gconstpointer watchdog)
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{
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const Watchdog *wd = watchdog;
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QTestState *qts = qtest_init("-machine quanta-gsj");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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watchdog_write_wtcr(qts, wd, WTCLK(1) | WTRF | WTIF | WTR);
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1));
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qtest_quit(qts);
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}
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/* Check a watchdog can generate interrupt and reset actions */
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static void test_reset_action(gconstpointer watchdog)
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{
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const Watchdog *wd = watchdog;
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QTestState *qts = qtest_init("-machine quanta-gsj");
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QDict *ad;
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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watchdog_write_wtcr(qts, wd,
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WTCLK(0) | WTE | WTRF | WTRE | WTIF | WTIE | WTR);
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
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WTCLK(0) | WTE | WTRE | WTIE);
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/* Check a watchdog can generate an interrupt */
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qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
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WTCLK(0) | WTE | WTIF | WTIE | WTRE);
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g_assert_true(qtest_get_irq(qts, wd->irq));
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/* Check a watchdog can generate a reset signal */
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qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
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watchdog_prescaler(qts, wd)));
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ad = get_watchdog_action(qts);
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/* The signal is a reset signal */
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g_assert_false(strcmp(qdict_get_str(ad, "action"), "reset"));
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qobject_unref(ad);
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qtest_qmp_eventwait(qts, "RESET");
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/*
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* Make sure WTCR is reset to default except for WTRF bit which shouldn't
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* be reset.
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*/
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1) | WTRF);
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qtest_quit(qts);
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}
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/* Check a watchdog works with all possible WTCLK prescalers and WTIS cycles */
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static void test_prescaler(gconstpointer watchdog)
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{
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const Watchdog *wd = watchdog;
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for (int wtclk = 0; wtclk < 4; ++wtclk) {
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for (int wtis = 0; wtis < 4; ++wtis) {
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QTestState *qts = qtest_init("-machine quanta-gsj");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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watchdog_write_wtcr(qts, wd,
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WTCLK(wtclk) | WTE | WTIF | WTIS(wtis) | WTIE | WTR);
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/*
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* The interrupt doesn't fire until watchdog_interrupt_steps()
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* cycles passed
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*/
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qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd) - 1);
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g_assert_false(watchdog_read_wtcr(qts, wd) & WTIF);
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g_assert_false(qtest_get_irq(qts, wd->irq));
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qtest_clock_step(qts, 1);
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g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
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g_assert_true(qtest_get_irq(qts, wd->irq));
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qtest_quit(qts);
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}
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}
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}
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/*
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* Check a watchdog doesn't fire if corresponding flags (WTIE and WTRE) are not
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* set.
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*/
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static void test_enabling_flags(gconstpointer watchdog)
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{
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const Watchdog *wd = watchdog;
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QTestState *qts;
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/* Neither WTIE or WTRE is set, no interrupt or reset should happen */
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qts = qtest_init("-machine quanta-gsj");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRF | WTR);
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qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
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g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
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g_assert_false(qtest_get_irq(qts, wd->irq));
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qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
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watchdog_prescaler(qts, wd)));
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g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
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g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
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qtest_quit(qts);
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/* Only WTIE is set, interrupt is triggered but reset should not happen */
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qts = qtest_init("-machine quanta-gsj");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
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qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
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g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
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g_assert_true(qtest_get_irq(qts, wd->irq));
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qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
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watchdog_prescaler(qts, wd)));
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g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
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g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
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qtest_quit(qts);
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/* Only WTRE is set, interrupt is triggered but reset should not happen */
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qts = qtest_init("-machine quanta-gsj");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRE | WTRF | WTR);
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qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
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g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
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g_assert_false(qtest_get_irq(qts, wd->irq));
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qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
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watchdog_prescaler(qts, wd)));
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g_assert_false(strcmp(qdict_get_str(get_watchdog_action(qts), "action"),
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"reset"));
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qtest_qmp_eventwait(qts, "RESET");
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qtest_quit(qts);
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/*
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* The case when both flags are set is already tested in
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* test_reset_action().
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*/
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}
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/* Check a watchdog can pause and resume by setting WTE bits */
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static void test_pause(gconstpointer watchdog)
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{
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const Watchdog *wd = watchdog;
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QTestState *qts;
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int64_t remaining_steps, steps;
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qts = qtest_init("-machine quanta-gsj");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
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remaining_steps = watchdog_interrupt_steps(qts, wd);
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
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/* Run for half of the execution period. */
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steps = remaining_steps / 2;
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remaining_steps -= steps;
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qtest_clock_step(qts, steps);
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/* Pause the watchdog */
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watchdog_write_wtcr(qts, wd, WTCLK(0) | WTIE);
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
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/* Run for a long period of time, the watchdog shouldn't fire */
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qtest_clock_step(qts, steps << 4);
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
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g_assert_false(qtest_get_irq(qts, wd->irq));
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/* Resume the watchdog */
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watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIE);
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
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/* Run for the reset of the execution period, the watchdog should fire */
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qtest_clock_step(qts, remaining_steps);
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g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
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WTCLK(0) | WTE | WTIF | WTIE);
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g_assert_true(qtest_get_irq(qts, wd->irq));
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qtest_quit(qts);
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}
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static void watchdog_add_test(const char *name, const Watchdog* wd,
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GTestDataFunc fn)
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{
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g_autofree char *full_name = g_strdup_printf(
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"npcm7xx_watchdog_timer[%d]/%s", watchdog_index(wd), name);
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qtest_add_data_func(full_name, wd, fn);
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}
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#define add_test(name, td) watchdog_add_test(#name, td, test_##name)
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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g_test_set_nonfatal_assertions();
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for (int i = 0; i < ARRAY_SIZE(watchdog_list); ++i) {
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const Watchdog *wd = &watchdog_list[i];
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add_test(init, wd);
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add_test(reset_action, wd);
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add_test(prescaler, wd);
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add_test(enabling_flags, wd);
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add_test(pause, wd);
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}
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return g_test_run();
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}
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