2005-07-02 16:58:51 +02:00
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#if !defined(__QEMU_MIPS_EXEC_H__)
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#define __QEMU_MIPS_EXEC_H__
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2005-12-17 02:11:12 +01:00
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//#define DEBUG_OP
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2005-07-02 16:58:51 +02:00
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2006-12-21 02:19:56 +01:00
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#include "config.h"
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2005-07-02 16:58:51 +02:00
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#include "mips-defs.h"
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#include "dyngen-exec.h"
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register struct CPUMIPSState *env asm(AREG0);
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#if defined (USE_64BITS_REGS)
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typedef int64_t host_int_t;
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typedef uint64_t host_uint_t;
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#else
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typedef int32_t host_int_t;
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typedef uint32_t host_uint_t;
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#endif
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2006-12-21 02:19:56 +01:00
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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#define T0 (env->t0)
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#define T1 (env->t1)
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#define T2 (env->t2)
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#else
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2005-07-02 16:58:51 +02:00
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register host_uint_t T0 asm(AREG1);
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register host_uint_t T1 asm(AREG2);
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register host_uint_t T2 asm(AREG3);
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2006-12-21 02:19:56 +01:00
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#endif
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2005-07-02 16:58:51 +02:00
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#if defined (USE_HOST_FLOAT_REGS)
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2006-06-14 14:56:19 +02:00
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#error "implement me."
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2005-07-02 16:58:51 +02:00
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#else
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2006-06-14 14:56:19 +02:00
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#define FDT0 (env->ft0.fd)
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#define FDT1 (env->ft1.fd)
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#define FDT2 (env->ft2.fd)
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#define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
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#define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
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#define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
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#define DT0 (env->ft0.d)
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#define DT1 (env->ft1.d)
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#define DT2 (env->ft2.d)
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#define WT0 (env->ft0.w[FP_ENDIAN_IDX])
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#define WT1 (env->ft1.w[FP_ENDIAN_IDX])
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#define WT2 (env->ft2.w[FP_ENDIAN_IDX])
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2005-07-02 16:58:51 +02:00
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#endif
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#if defined (DEBUG_OP)
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2006-12-23 01:49:32 +01:00
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# define RETURN() __asm__ __volatile__("nop" : : : "memory");
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2005-07-02 16:58:51 +02:00
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#else
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2006-12-23 01:49:32 +01:00
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# define RETURN() __asm__ __volatile__("" : : : "memory");
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2005-07-02 16:58:51 +02:00
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#endif
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#include "cpu.h"
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#include "exec-all.h"
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#if !defined(CONFIG_USER_ONLY)
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2005-10-30 19:16:26 +01:00
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#include "softmmu_exec.h"
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2005-07-02 16:58:51 +02:00
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#endif /* !defined(CONFIG_USER_ONLY) */
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static inline void env_to_regs(void)
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{
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}
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static inline void regs_to_env(void)
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{
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}
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2007-04-01 14:36:18 +02:00
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#ifdef TARGET_MIPS64
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2006-12-21 02:19:56 +01:00
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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void do_dsll (void);
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void do_dsll32 (void);
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void do_dsra (void);
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void do_dsra32 (void);
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void do_dsrl (void);
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void do_dsrl32 (void);
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void do_drotr (void);
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void do_drotr32 (void);
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void do_dsllv (void);
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void do_dsrav (void);
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void do_dsrlv (void);
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void do_drotrv (void);
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#endif
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#endif
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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2005-07-02 16:58:51 +02:00
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void do_mult (void);
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void do_multu (void);
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void do_madd (void);
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void do_maddu (void);
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void do_msub (void);
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void do_msubu (void);
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2006-12-21 02:19:56 +01:00
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void do_ddiv (void);
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void do_ddivu (void);
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#endif
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2007-04-01 14:36:18 +02:00
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#ifdef TARGET_MIPS64
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2006-12-21 02:19:56 +01:00
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void do_dmult (void);
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void do_dmultu (void);
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2005-07-02 16:58:51 +02:00
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#endif
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2006-12-06 18:59:07 +01:00
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void do_mfc0_random(void);
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void do_mfc0_count(void);
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2006-12-06 21:17:30 +01:00
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void do_mtc0_entryhi(uint32_t in);
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2006-12-06 19:19:33 +01:00
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void do_mtc0_status_debug(uint32_t old, uint32_t val);
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void do_mtc0_status_irqraise_debug(void);
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2005-07-02 16:58:51 +02:00
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void do_tlbwi (void);
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void do_tlbwr (void);
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void do_tlbp (void);
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void do_tlbr (void);
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2006-06-14 14:56:19 +02:00
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void dump_fpu(CPUState *env);
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void fpu_dump_state(CPUState *env, FILE *f,
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int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
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int flags);
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void dump_sc (void);
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2005-12-05 20:59:36 +01:00
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void do_lwl_raw (uint32_t);
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void do_lwr_raw (uint32_t);
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uint32_t do_swl_raw (uint32_t);
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uint32_t do_swr_raw (uint32_t);
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2007-04-01 14:36:18 +02:00
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#ifdef TARGET_MIPS64
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2006-12-21 02:19:56 +01:00
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void do_ldl_raw (uint64_t);
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void do_ldr_raw (uint64_t);
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uint64_t do_sdl_raw (uint64_t);
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uint64_t do_sdr_raw (uint64_t);
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#endif
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2005-07-02 16:58:51 +02:00
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#if !defined(CONFIG_USER_ONLY)
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2005-12-05 20:59:36 +01:00
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void do_lwl_user (uint32_t);
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void do_lwl_kernel (uint32_t);
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void do_lwr_user (uint32_t);
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void do_lwr_kernel (uint32_t);
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uint32_t do_swl_user (uint32_t);
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uint32_t do_swl_kernel (uint32_t);
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uint32_t do_swr_user (uint32_t);
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uint32_t do_swr_kernel (uint32_t);
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2007-04-01 14:36:18 +02:00
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#ifdef TARGET_MIPS64
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2006-12-21 02:19:56 +01:00
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void do_ldl_user (uint64_t);
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void do_ldl_kernel (uint64_t);
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void do_ldr_user (uint64_t);
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void do_ldr_kernel (uint64_t);
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uint64_t do_sdl_user (uint64_t);
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uint64_t do_sdl_kernel (uint64_t);
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uint64_t do_sdr_user (uint64_t);
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uint64_t do_sdr_kernel (uint64_t);
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#endif
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2005-07-02 16:58:51 +02:00
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#endif
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void do_pmon (int function);
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2006-03-11 16:00:08 +01:00
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void dump_sc (void);
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2005-07-02 16:58:51 +02:00
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu);
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void do_interrupt (CPUState *env);
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2007-01-03 16:18:08 +01:00
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void invalidate_tlb (CPUState *env, int idx, int use_extra);
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2005-07-02 16:58:51 +02:00
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void cpu_loop_exit(void);
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void do_raise_exception_err (uint32_t exception, int error_code);
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void do_raise_exception (uint32_t exception);
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2007-03-23 01:43:28 +01:00
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void do_raise_exception_direct_err (uint32_t exception, int error_code);
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2005-12-05 20:59:36 +01:00
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void do_raise_exception_direct (uint32_t exception);
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2005-07-02 16:58:51 +02:00
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void cpu_dump_state(CPUState *env, FILE *f,
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int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
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int flags);
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void cpu_mips_irqctrl_init (void);
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uint32_t cpu_mips_get_random (CPUState *env);
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uint32_t cpu_mips_get_count (CPUState *env);
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void cpu_mips_store_count (CPUState *env, uint32_t value);
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void cpu_mips_store_compare (CPUState *env, uint32_t value);
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2007-03-31 18:54:14 +02:00
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void cpu_mips_update_irq (CPUState *env);
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2005-07-02 16:58:51 +02:00
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void cpu_mips_clock_init (CPUState *env);
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2006-12-06 18:42:40 +01:00
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void cpu_mips_tlb_flush (CPUState *env, int flush_global);
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2005-07-02 16:58:51 +02:00
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#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
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