2016-03-16 18:06:01 +01:00
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/*
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* OpenPOWER Palmetto BMC
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2019-05-23 15:47:43 +02:00
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#include "hw/arm/boot.h"
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2018-09-25 15:02:33 +02:00
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#include "hw/arm/aspeed.h"
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2016-09-22 19:13:05 +02:00
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#include "hw/arm/aspeed_soc.h"
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2023-02-07 09:02:05 +01:00
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#include "hw/arm/aspeed_eeprom.h"
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2021-06-08 22:25:22 +02:00
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#include "hw/i2c/i2c_mux_pca954x.h"
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2018-11-14 01:31:27 +01:00
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#include "hw/i2c/smbus_eeprom.h"
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2019-04-12 18:54:05 +02:00
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#include "hw/misc/pca9552.h"
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2023-02-07 09:02:04 +01:00
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#include "hw/nvram/eeprom_at24c.h"
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2021-05-18 23:08:03 +02:00
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#include "hw/sensor/tmp105.h"
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2020-06-20 18:54:41 +02:00
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#include "hw/misc/led.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2016-07-04 14:06:38 +02:00
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#include "sysemu/block-backend.h"
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2022-05-25 10:31:33 +02:00
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#include "sysemu/reset.h"
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2017-01-20 12:15:08 +01:00
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#include "hw/loader.h"
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#include "qemu/error-report.h"
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2019-05-07 13:55:02 +02:00
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#include "qemu/units.h"
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2022-05-02 17:03:03 +02:00
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#include "hw/qdev-clock.h"
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aspeed: Refactor UART init for multi-SoC machines
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allow multi-SoC
boards to completely change the wiring of serial devices from the
command line to specific SoC UART's.
This also removes the uart-default property from the SoC, since the SoC
doesn't need to know what UART is the "default" on the machine anymore.
I tested this using the images and commands from the previous
refactoring, and another test image for the ast1030:
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Fuji uses UART1:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
ast2600-evb uses uart-default=UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
Wedge100 uses UART3:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
AST1030 EVB uses UART5:
qemu-system-arm -machine ast1030-evb \
-kernel Y35BCL.elf -nographic
Fixes: 6827ff20b2975 ("hw: aspeed: Init all UART's with serial devices")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-07-14 16:24:38 +02:00
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#include "sysemu/sysemu.h"
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2016-03-16 18:06:01 +01:00
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2016-09-22 19:13:05 +02:00
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static struct arm_boot_info aspeed_board_binfo = {
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2016-09-22 19:13:05 +02:00
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.board_id = -1, /* device-tree-only board */
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2016-03-16 18:06:01 +01:00
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};
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2020-06-23 09:21:31 +02:00
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struct AspeedMachineState {
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2020-06-23 09:21:32 +02:00
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/* Private */
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MachineState parent_obj;
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/* Public */
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2016-09-22 19:13:05 +02:00
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AspeedSoCState soc;
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2020-06-23 09:21:32 +02:00
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bool mmio_exec;
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2020-09-18 09:04:36 +02:00
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char *fmc_model;
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char *spi_model;
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2018-11-28 10:35:36 +01:00
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};
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2016-03-16 18:06:01 +01:00
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2016-12-27 15:59:27 +01:00
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/* Palmetto hardware value: 0x120CE416 */
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2016-09-22 19:13:05 +02:00
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#define PALMETTO_BMC_HW_STRAP1 ( \
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SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
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SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
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SCU_AST2400_HW_STRAP_ACPI_DIS | \
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SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
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SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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2020-09-01 14:21:50 +02:00
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/* TODO: Find the actual hardware value */
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#define SUPERMICROX11_BMC_HW_STRAP1 ( \
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SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
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SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
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SCU_AST2400_HW_STRAP_ACPI_DIS | \
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SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
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SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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2023-02-07 09:02:04 +01:00
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/* TODO: Find the actual hardware value */
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#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
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2016-12-27 15:59:27 +01:00
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/* AST2500 evb hardware value: 0xF100C2E6 */
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2016-09-22 19:13:06 +02:00
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#define AST2500_EVB_HW_STRAP1 (( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_MAC1_RGMII | \
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SCU_HW_STRAP_MAC0_RGMII) & \
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~SCU_HW_STRAP_2ND_BOOT_WDT)
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2016-12-27 15:59:27 +01:00
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/* Romulus hardware value: 0xF10AD206 */
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#define ROMULUS_BMC_HW_STRAP1 ( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
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2020-05-06 20:32:19 +02:00
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/* Sonorapass hardware value: 0xF100D216 */
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#define SONORAPASS_BMC_HW_STRAP1 ( \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_RESERVED28 | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
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SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_VGA_BIOS_ROM | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2500_HW_STRAP_RESERVED1)
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2020-12-10 12:11:03 +01:00
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#define G220A_BMC_HW_STRAP1 ( \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_RESERVED28 | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_2ND_BOOT_WDT | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
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SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
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SCU_AST2500_HW_STRAP_RESERVED1)
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2021-10-22 09:52:16 +02:00
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/* FP5280G2 hardware value: 0XF100D286 */
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#define FP5280G2_BMC_HW_STRAP1 ( \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_RESERVED28 | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
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SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_MAC1_RGMII | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2500_HW_STRAP_RESERVED1)
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2018-06-08 14:15:32 +02:00
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/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
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#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
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2021-05-01 10:03:52 +02:00
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/* Quanta-Q71l hardware value */
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#define QUANTA_Q71L_BMC_HW_STRAP1 ( \
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SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
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SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
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SCU_AST2400_HW_STRAP_ACPI_DIS | \
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SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
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SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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2019-10-23 15:04:55 +02:00
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/* AST2600 evb hardware value */
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#define AST2600_EVB_HW_STRAP1 0x000000C0
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#define AST2600_EVB_HW_STRAP2 0x00000003
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2019-11-19 15:12:08 +01:00
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/* Tacoma hardware value */
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#define TACOMA_BMC_HW_STRAP1 0x00000000
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2020-05-04 11:37:03 +02:00
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#define TACOMA_BMC_HW_STRAP2 0x00000040
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2019-11-19 15:12:08 +01:00
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2021-05-01 10:03:52 +02:00
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/* Rainier hardware value: (QEMU prototype) */
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2022-02-18 09:18:12 +01:00
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#define RAINIER_BMC_HW_STRAP1 0x00422016
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#define RAINIER_BMC_HW_STRAP2 0x80000848
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2021-05-01 10:03:52 +02:00
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2021-09-20 08:50:59 +02:00
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/* Fuji hardware value */
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#define FUJI_BMC_HW_STRAP1 0x00000000
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#define FUJI_BMC_HW_STRAP2 0x00000000
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2022-03-08 09:18:11 +01:00
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/* Bletchley hardware value */
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/* TODO: Leave same as EVB for now. */
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#define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
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#define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
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2022-06-30 09:21:13 +02:00
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/* Qualcomm DC-SCM hardware value */
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#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
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#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
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2020-04-09 08:31:37 +02:00
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#define AST_SMP_MAILBOX_BASE 0x1e6e2180
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#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
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#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
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#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
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#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
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#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
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#define AST_SMP_MBOX_GOSIGN 0xabbaab00
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static void aspeed_write_smpboot(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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2023-04-24 17:27:16 +02:00
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AddressSpace *as = arm_boot_address_space(cpu, info);
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static const ARMInsnFixup poll_mailbox_ready[] = {
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2020-04-09 08:31:37 +02:00
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/*
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* r2 = per-cpu go sign value
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* r1 = AST_SMP_MBOX_FIELD_ENTRY
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* r0 = AST_SMP_MBOX_FIELD_GOSIGN
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*/
|
2023-04-24 17:27:16 +02:00
|
|
|
{ 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
|
|
|
|
{ 0xe21000ff }, /* ands r0, r0, #255 */
|
|
|
|
{ 0xe59f201c }, /* ldr r2, [pc, #28] */
|
|
|
|
{ 0xe1822000 }, /* orr r2, r2, r0 */
|
|
|
|
|
|
|
|
{ 0xe59f1018 }, /* ldr r1, [pc, #24] */
|
|
|
|
{ 0xe59f0018 }, /* ldr r0, [pc, #24] */
|
|
|
|
|
|
|
|
{ 0xe320f002 }, /* wfe */
|
|
|
|
{ 0xe5904000 }, /* ldr r4, [r0] */
|
|
|
|
{ 0xe1520004 }, /* cmp r2, r4 */
|
|
|
|
{ 0x1afffffb }, /* bne <wfe> */
|
|
|
|
{ 0xe591f000 }, /* ldr pc, [r1] */
|
|
|
|
{ AST_SMP_MBOX_GOSIGN },
|
|
|
|
{ AST_SMP_MBOX_FIELD_ENTRY },
|
|
|
|
{ AST_SMP_MBOX_FIELD_GOSIGN },
|
|
|
|
{ 0, FIXUP_TERMINATOR }
|
2020-04-09 08:31:37 +02:00
|
|
|
};
|
2023-04-24 17:27:16 +02:00
|
|
|
static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
|
2020-04-09 08:31:37 +02:00
|
|
|
|
2023-04-24 17:27:16 +02:00
|
|
|
arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
|
|
|
|
poll_mailbox_ready, fixupcontext);
|
2020-04-09 08:31:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_reset_secondary(ARMCPU *cpu,
|
|
|
|
const struct arm_boot_info *info)
|
|
|
|
{
|
|
|
|
AddressSpace *as = arm_boot_address_space(cpu, info);
|
|
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
|
|
|
|
/* info->smp_bootreg_addr */
|
|
|
|
address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
|
|
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
|
|
cpu_set_pc(cs, info->smp_loader_start);
|
|
|
|
}
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
|
2017-01-20 12:15:08 +01:00
|
|
|
Error **errp)
|
|
|
|
{
|
2022-03-08 09:18:11 +01:00
|
|
|
g_autofree void *storage = NULL;
|
2017-02-10 18:40:29 +01:00
|
|
|
int64_t size;
|
|
|
|
|
|
|
|
/* The block backend size should have already been 'validated' by
|
|
|
|
* the creation of the m25p80 object.
|
|
|
|
*/
|
|
|
|
size = blk_getlength(blk);
|
|
|
|
if (size <= 0) {
|
|
|
|
error_setg(errp, "failed to get flash size");
|
|
|
|
return;
|
|
|
|
}
|
2017-01-20 12:15:08 +01:00
|
|
|
|
2017-02-10 18:40:29 +01:00
|
|
|
if (rom_size > size) {
|
|
|
|
rom_size = size;
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
|
|
|
|
2022-03-08 09:18:11 +01:00
|
|
|
storage = g_malloc0(rom_size);
|
block: Change blk_{pread,pwrite}() param order
Swap 'buf' and 'bytes' around for consistency with
blk_co_{pread,pwrite}(), and in preparation to implement these functions
using generated_co_wrapper.
Callers were updated using this Coccinelle script:
@@ expression blk, offset, buf, bytes, flags; @@
- blk_pread(blk, offset, buf, bytes, flags)
+ blk_pread(blk, offset, bytes, buf, flags)
@@ expression blk, offset, buf, bytes, flags; @@
- blk_pwrite(blk, offset, buf, bytes, flags)
+ blk_pwrite(blk, offset, bytes, buf, flags)
It had no effect on hw/block/nand.c, presumably due to the #if, so that
file was updated manually.
Overly-long lines were then fixed by hand.
Signed-off-by: Alberto Faria <afaria@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220705161527.1054072-4-afaria@redhat.com>
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2022-07-05 18:15:11 +02:00
|
|
|
if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
|
2017-01-20 12:15:08 +01:00
|
|
|
error_setg(errp, "failed to read the initial flash content");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
|
|
|
|
}
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
/*
|
|
|
|
* Create a ROM and copy the flash contents at the expected address
|
|
|
|
* (0x0). Boots faster than execute-in-place.
|
|
|
|
*/
|
|
|
|
static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
|
|
|
|
uint64_t rom_size)
|
|
|
|
{
|
|
|
|
MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
|
|
|
|
|
|
|
|
memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size,
|
|
|
|
&error_abort);
|
|
|
|
memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
|
|
|
|
boot_rom, 1);
|
|
|
|
write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
|
|
|
|
}
|
|
|
|
|
2022-07-14 16:24:38 +02:00
|
|
|
void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
|
2022-03-08 09:18:11 +01:00
|
|
|
unsigned int count, int unit0)
|
2016-07-04 14:06:38 +02:00
|
|
|
{
|
2022-03-08 09:18:11 +01:00
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!flashtype) {
|
|
|
|
return;
|
|
|
|
}
|
2016-07-04 14:06:38 +02:00
|
|
|
|
2022-03-08 09:18:11 +01:00
|
|
|
for (i = 0; i < count; ++i) {
|
2021-11-17 17:34:08 +01:00
|
|
|
DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
|
2016-07-04 14:06:38 +02:00
|
|
|
qemu_irq cs_line;
|
2021-10-12 08:20:08 +02:00
|
|
|
DeviceState *dev;
|
2016-07-04 14:06:38 +02:00
|
|
|
|
2021-10-12 08:20:08 +02:00
|
|
|
dev = qdev_new(flashtype);
|
2016-07-04 14:06:38 +02:00
|
|
|
if (dinfo) {
|
2021-10-12 08:20:08 +02:00
|
|
|
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
2021-10-12 08:20:08 +02:00
|
|
|
qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
|
2016-07-04 14:06:38 +02:00
|
|
|
|
2021-10-12 08:20:08 +02:00
|
|
|
cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
|
2023-03-02 13:57:50 +01:00
|
|
|
qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
|
|
|
|
{
|
|
|
|
DeviceState *card;
|
|
|
|
|
2020-07-13 15:36:12 +02:00
|
|
|
if (!dinfo) {
|
|
|
|
return;
|
2020-01-30 17:02:02 +01:00
|
|
|
}
|
2020-07-13 15:36:12 +02:00
|
|
|
card = qdev_new(TYPE_SD_CARD);
|
|
|
|
qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
|
|
|
|
&error_fatal);
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
qdev_realize_and_unref(card,
|
|
|
|
qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
|
|
|
|
&error_fatal);
|
2020-01-30 17:02:02 +01:00
|
|
|
}
|
|
|
|
|
aspeed: Refactor UART init for multi-SoC machines
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allow multi-SoC
boards to completely change the wiring of serial devices from the
command line to specific SoC UART's.
This also removes the uart-default property from the SoC, since the SoC
doesn't need to know what UART is the "default" on the machine anymore.
I tested this using the images and commands from the previous
refactoring, and another test image for the ast1030:
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Fuji uses UART1:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
ast2600-evb uses uart-default=UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
Wedge100 uses UART3:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
AST1030 EVB uses UART5:
qemu-system-arm -machine ast1030-evb \
-kernel Y35BCL.elf -nographic
Fixes: 6827ff20b2975 ("hw: aspeed: Init all UART's with serial devices")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-07-14 16:24:38 +02:00
|
|
|
static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
|
|
|
|
AspeedSoCState *s = &bmc->soc;
|
|
|
|
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
|
|
|
|
|
|
|
|
aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
|
|
|
|
for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
|
|
|
|
if (uart == amc->uart_default) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_init(MachineState *machine)
|
2016-03-16 18:06:01 +01:00
|
|
|
{
|
2020-06-23 09:21:32 +02:00
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(machine);
|
2019-11-19 15:12:07 +01:00
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
|
2016-09-22 19:13:05 +02:00
|
|
|
AspeedSoCClass *sc;
|
2019-09-25 16:32:27 +02:00
|
|
|
int i;
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
NICInfo *nd = &nd_table[0];
|
2016-03-16 18:06:01 +01:00
|
|
|
|
qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument. Almost all pass &error_abort and no properties. Tiresome.
Rename object_initialize_child() to
object_initialize_child_with_props() to free the name. New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.
Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.
Convert callers with this Coccinelle script:
@@
expression parent, propname, type;
expression child, size;
symbol error_abort;
@@
- object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, &child, type)
@@
expression parent, propname, type;
expression child, size, err;
expression list props;
@@
- object_initialize_child(parent, propname, child, size, type, err, props)
+ object_initialize_child_with_props(parent, propname, child, size, type, err, props)
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e7)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 07:32:25 +02:00
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object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
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2016-03-16 18:06:01 +01:00
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2016-09-22 19:13:05 +02:00
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sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
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2020-02-19 17:08:43 +01:00
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/*
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2022-06-30 09:21:13 +02:00
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* This will error out if the RAM size is not supported by the
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* memory controller of the SoC.
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2020-02-19 17:08:43 +01:00
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*/
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2020-10-28 11:18:20 +01:00
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object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
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2020-02-19 17:08:43 +01:00
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&error_fatal);
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arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
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for (i = 0; i < sc->macs_num; i++) {
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if ((amc->macs_mask & (1 << i)) && nd->used) {
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qemu_check_nic_model(nd, TYPE_FTGMAC100);
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qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
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nd++;
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}
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}
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qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
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object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
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2016-06-27 16:37:33 +02:00
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&error_abort);
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qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
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object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
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2019-10-23 15:04:55 +02:00
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&error_abort);
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2022-06-30 09:21:13 +02:00
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object_property_set_link(OBJECT(&bmc->soc), "memory",
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OBJECT(get_system_memory()), &error_abort);
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qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
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object_property_set_link(OBJECT(&bmc->soc), "dram",
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2021-05-01 10:03:51 +02:00
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OBJECT(machine->ram), &error_abort);
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2017-11-14 13:20:18 +01:00
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if (machine->kernel_filename) {
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/*
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* When booting with a -kernel command line there is no u-boot
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* that runs to unlock the SCU. In this case set the default to
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* be unlocked as the kernel expects
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*/
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qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
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object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
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ASPEED_SCU_PROT_KEY, &error_abort);
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2017-11-14 13:20:18 +01:00
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}
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aspeed: Refactor UART init for multi-SoC machines
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allow multi-SoC
boards to completely change the wiring of serial devices from the
command line to specific SoC UART's.
This also removes the uart-default property from the SoC, since the SoC
doesn't need to know what UART is the "default" on the machine anymore.
I tested this using the images and commands from the previous
refactoring, and another test image for the ast1030:
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Fuji uses UART1:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
ast2600-evb uses uart-default=UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
Wedge100 uses UART3:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
AST1030 EVB uses UART5:
qemu-system-arm -machine ast1030-evb \
-kernel Y35BCL.elf -nographic
Fixes: 6827ff20b2975 ("hw: aspeed: Init all UART's with serial devices")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-07-14 16:24:38 +02:00
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connect_serial_hds_to_uarts(bmc);
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qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 07:32:45 +02:00
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qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
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2016-03-16 18:06:01 +01:00
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2021-11-17 17:34:08 +01:00
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aspeed_board_init_flashes(&bmc->soc.fmc,
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bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
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2022-03-08 09:18:11 +01:00
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amc->num_cs, 0);
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2021-11-17 17:34:08 +01:00
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aspeed_board_init_flashes(&bmc->soc.spi[0],
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bmc->spi_model ? bmc->spi_model : amc->spi_model,
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2022-03-08 09:18:11 +01:00
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1, amc->num_cs);
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2016-09-22 19:13:05 +02:00
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arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
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if (machine->kernel_filename && sc->num_cpus > 1) {
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2020-04-09 08:31:37 +02:00
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/* With no u-boot we must set up a boot stub for the secondary CPU */
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MemoryRegion *smpboot = g_new(MemoryRegion, 1);
|
hw/arm/aspeed: Remove extraneous MemoryRegion object owner
I'm confused by this code, 'bmc' is created as:
bmc = g_new0(AspeedBoardState, 1);
Then we use it as QOM owner for different MemoryRegion objects.
But looking at memory_region_init_ram (similarly for ROM):
void memory_region_init_ram(MemoryRegion *mr,
struct Object *owner,
const char *name,
uint64_t size,
Error **errp)
{
DeviceState *owner_dev;
Error *err = NULL;
memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
if (err) {
error_propagate(errp, err);
return;
}
/* This will assert if owner is neither NULL nor a DeviceState.
* We only want the owner here for the purposes of defining a
* unique name for migration. TODO: Ideally we should implement
* a naming scheme for Objects which are not DeviceStates, in
* which case we can relax this restriction.
*/
owner_dev = DEVICE(owner);
vmstate_register_ram(mr, owner_dev);
}
The expected assertion is not triggered ('bmc' is not NULL neither
a DeviceState).
'bmc' structure is defined as:
struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram_container;
MemoryRegion max_ram;
};
What happens is when using 'OBJECT(bmc)', the QOM macros cast the
memory pointed by bmc, which first member is 'soc', which is
initialized ...:
object_initialize_child(OBJECT(machine), "soc",
&bmc->soc, amc->soc_name);
The 'soc' object is indeed a DeviceState, so the assertion passes.
Since this is fragile and only happens to work by luck, remove the
dangerous OBJECT(bmc) owner argument.
Note, this probably breaks migration for this machine.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200623072132.2868-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 09:21:30 +02:00
|
|
|
memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
|
2020-04-09 08:31:37 +02:00
|
|
|
0x80, &error_abort);
|
|
|
|
memory_region_add_subregion(get_system_memory(),
|
|
|
|
AST_SMP_MAILBOX_BASE, smpboot);
|
|
|
|
|
|
|
|
aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
|
|
|
|
aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
|
|
|
|
aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
|
|
|
|
}
|
|
|
|
|
2020-10-28 11:18:20 +01:00
|
|
|
aspeed_board_binfo.ram_size = machine->ram_size;
|
2020-08-25 21:20:02 +02:00
|
|
|
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
|
2016-07-04 14:06:38 +02:00
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
if (amc->i2c_init) {
|
|
|
|
amc->i2c_init(bmc);
|
2017-06-02 12:51:49 +02:00
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
|
2021-11-17 17:34:08 +01:00
|
|
|
sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
|
|
|
|
drive_get(IF_SD, 0, i));
|
2020-01-30 17:02:02 +01:00
|
|
|
}
|
2019-09-25 16:32:27 +02:00
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
if (bmc->soc.emmc.num_slots) {
|
2021-11-17 17:34:08 +01:00
|
|
|
sdhci_attach_drive(&bmc->soc.emmc.slots[0],
|
|
|
|
drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
|
2019-09-25 16:32:27 +02:00
|
|
|
}
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
if (!bmc->mmio_exec) {
|
|
|
|
DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
|
|
|
|
|
|
|
|
if (mtd0) {
|
|
|
|
uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
|
|
|
|
aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0),
|
|
|
|
rom_size);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-08-09 08:57:21 +02:00
|
|
|
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
|
2016-09-22 19:13:05 +02:00
|
|
|
}
|
2016-09-22 19:13:05 +02:00
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
|
2017-06-02 12:51:49 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2017-06-13 15:56:59 +02:00
|
|
|
DeviceState *dev;
|
2018-06-08 14:15:32 +02:00
|
|
|
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
|
2017-06-02 12:51:49 +02:00
|
|
|
|
|
|
|
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
|
|
|
|
* enough to provide basic RTC features. Alarms will be missing */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
|
2017-06-13 15:56:59 +02:00
|
|
|
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
|
2018-06-08 14:15:32 +02:00
|
|
|
eeprom_buf);
|
|
|
|
|
2017-06-13 15:56:59 +02:00
|
|
|
/* add a TMP423 temperature sensor */
|
2020-07-06 00:41:53 +02:00
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
|
|
|
|
"tmp423", 0x4c));
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
|
2017-06-02 12:51:49 +02:00
|
|
|
}
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The quanta-q71l platform expects tmp75s which are compatible with
|
|
|
|
* tmp105s.
|
|
|
|
*/
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
|
|
|
|
|
|
|
|
/* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
|
|
|
|
/* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
|
|
|
|
/* TODO: Add Memory Riser i2c mux and eeproms. */
|
|
|
|
|
2021-06-08 22:25:22 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
/* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
|
2021-06-08 22:25:22 +02:00
|
|
|
|
|
|
|
/* i2c-7 */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
|
2021-05-01 10:03:52 +02:00
|
|
|
/* - i2c@0: pmbus@59 */
|
|
|
|
/* - i2c@1: pmbus@58 */
|
|
|
|
/* - i2c@2: pmbus@58 */
|
|
|
|
/* - i2c@3: pmbus@59 */
|
2021-06-08 22:25:22 +02:00
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
/* TODO: i2c-7: Add PDB FRU eeprom@52 */
|
|
|
|
/* TODO: i2c-8: Add BMC FRU eeprom@50 */
|
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
|
2017-06-02 12:51:49 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2018-06-08 14:15:32 +02:00
|
|
|
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
|
|
|
|
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
|
2018-06-08 14:15:32 +02:00
|
|
|
eeprom_buf);
|
2017-06-02 12:51:49 +02:00
|
|
|
|
|
|
|
/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
|
2019-04-12 18:54:05 +02:00
|
|
|
TYPE_TMP105, 0x4d);
|
2017-06-02 12:51:49 +02:00
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
|
2019-10-23 15:04:55 +02:00
|
|
|
{
|
2022-05-25 12:00:01 +02:00
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
|
|
|
|
|
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
|
|
|
|
eeprom_buf);
|
|
|
|
|
|
|
|
/* LM75 is compatible with TMP105 driver */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
|
|
|
|
TYPE_TMP105, 0x4d);
|
2019-10-23 15:04:55 +02:00
|
|
|
}
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
|
|
|
|
at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
|
|
|
|
yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
|
2023-03-07 16:53:18 +01:00
|
|
|
/* TMP421 */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
|
2018-06-08 14:15:32 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
/* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
|
|
|
|
* good enough */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
|
2018-06-08 14:15:32 +02:00
|
|
|
}
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
|
|
|
|
at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
|
|
|
|
tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
|
2023-03-07 16:53:18 +01:00
|
|
|
/* TMP421 */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
|
2023-03-02 13:57:50 +01:00
|
|
|
}
|
|
|
|
|
2022-02-18 09:18:13 +01:00
|
|
|
static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
|
|
|
|
{
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
|
|
|
|
TYPE_PCA9552, addr);
|
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
|
2020-05-06 20:32:19 +02:00
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
/* bus 2 : */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* bus 2 : pca9546 @ 0x73 */
|
|
|
|
|
|
|
|
/* bus 3 : pca9548 @ 0x70 */
|
|
|
|
|
|
|
|
/* bus 4 : */
|
|
|
|
uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
|
2020-05-06 20:32:19 +02:00
|
|
|
eeprom4_54);
|
|
|
|
/* PCA9539 @ 0x76, but PCA9552 is compatible */
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 4, 0x76);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* PCA9539 @ 0x77, but PCA9552 is compatible */
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 4, 0x77);
|
2020-05-06 20:32:19 +02:00
|
|
|
|
|
|
|
/* bus 6 : */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* bus 6 : pca9546 @ 0x73 */
|
|
|
|
|
|
|
|
/* bus 8 : */
|
|
|
|
uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
|
2020-05-06 20:32:19 +02:00
|
|
|
eeprom8_56);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 8, 0x60);
|
|
|
|
create_pca9552(soc, 8, 0x61);
|
2020-05-06 20:32:19 +02:00
|
|
|
/* bus 8 : adc128d818 @ 0x1d */
|
|
|
|
/* bus 8 : adc128d818 @ 0x1f */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* bus 13 : pca9548 @ 0x71
|
|
|
|
* - channel 3:
|
|
|
|
* - tmm421 @ 0x4c
|
|
|
|
* - tmp421 @ 0x4e
|
|
|
|
* - tmp421 @ 0x4f
|
|
|
|
*/
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2020-06-23 09:21:31 +02:00
|
|
|
static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
|
2018-06-08 14:15:32 +02:00
|
|
|
{
|
2020-06-20 18:54:41 +02:00
|
|
|
static const struct {
|
|
|
|
unsigned gpio_id;
|
|
|
|
LEDColor color;
|
|
|
|
const char *description;
|
|
|
|
bool gpio_polarity;
|
|
|
|
} pca1_leds[] = {
|
|
|
|
{13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
|
|
|
|
{14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
|
|
|
|
{15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
|
|
|
|
};
|
2018-06-08 14:15:32 +02:00
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2018-06-08 14:15:32 +02:00
|
|
|
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
|
2020-06-23 09:27:21 +02:00
|
|
|
DeviceState *dev;
|
2020-06-20 18:54:41 +02:00
|
|
|
LEDState *led;
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2019-11-19 15:12:08 +01:00
|
|
|
/* Bus 3: TODO bmp280@77 */
|
2020-07-06 00:41:51 +02:00
|
|
|
dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
|
2020-06-23 09:27:21 +02:00
|
|
|
qdev_prop_set_string(dev, "description", "pca1");
|
2020-07-06 00:41:52 +02:00
|
|
|
i2c_slave_realize_and_unref(I2C_SLAVE(dev),
|
|
|
|
aspeed_i2c_get_bus(&soc->i2c, 3),
|
|
|
|
&error_fatal);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2020-06-20 18:54:41 +02:00
|
|
|
for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
|
|
|
|
led = led_create_simple(OBJECT(bmc),
|
|
|
|
pca1_leds[i].gpio_polarity,
|
|
|
|
pca1_leds[i].color,
|
|
|
|
pca1_leds[i].description);
|
|
|
|
qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
|
|
|
|
qdev_get_gpio_in(DEVICE(led), 0));
|
|
|
|
}
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
|
2022-06-30 09:21:13 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
|
|
|
/* The Witherspoon expects a TMP275 but a TMP105 is compatible */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
|
2019-04-12 18:54:05 +02:00
|
|
|
0x4a);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
|
|
|
/* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
|
|
|
|
* good enough */
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2020-07-06 00:41:50 +02:00
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
|
2018-06-08 14:15:32 +02:00
|
|
|
eeprom_buf);
|
2020-07-06 00:41:51 +02:00
|
|
|
dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
|
2020-06-23 09:27:21 +02:00
|
|
|
qdev_prop_set_string(dev, "description", "pca0");
|
2020-07-06 00:41:52 +02:00
|
|
|
i2c_slave_realize_and_unref(I2C_SLAVE(dev),
|
|
|
|
aspeed_i2c_get_bus(&soc->i2c, 11),
|
|
|
|
&error_fatal);
|
2019-11-19 15:12:08 +01:00
|
|
|
/* Bus 11: TODO ucd90160@64 */
|
2018-06-08 14:15:32 +02:00
|
|
|
}
|
|
|
|
|
2020-12-10 12:11:03 +01:00
|
|
|
static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
DeviceState *dev;
|
|
|
|
|
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
|
|
|
|
"emc1413", 0x4c));
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
|
|
|
|
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
|
|
|
|
"emc1413", 0x4c));
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
|
|
|
|
|
|
|
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
|
|
|
|
"emc1413", 0x4c));
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
|
|
|
|
object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
|
2020-12-10 12:11:03 +01:00
|
|
|
|
|
|
|
static uint8_t eeprom_buf[2 * 1024] = {
|
|
|
|
0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
|
|
|
|
0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
|
|
|
|
0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
|
|
|
|
0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
|
|
|
|
0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
|
|
|
|
0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
|
|
|
|
};
|
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
|
|
|
|
eeprom_buf);
|
2020-12-10 12:11:03 +01:00
|
|
|
}
|
|
|
|
|
2021-10-22 09:52:16 +02:00
|
|
|
static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
I2CSlave *i2c_mux;
|
|
|
|
|
|
|
|
/* The at24c256 */
|
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
|
|
|
|
|
|
|
|
/* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
|
|
|
|
0x49);
|
|
|
|
|
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
|
|
|
|
"pca9546", 0x70);
|
|
|
|
/* It expects a TMP112 but a TMP105 is compatible */
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
|
|
|
|
0x4a);
|
|
|
|
|
|
|
|
/* It expects a ds3232 but a ds1338 is good enough */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
|
|
|
|
|
|
|
|
/* It expects a pca9555 but a pca9552 is compatible */
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 8, 0x30);
|
2021-10-22 09:52:16 +02:00
|
|
|
}
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2021-09-20 08:50:59 +02:00
|
|
|
I2CSlave *i2c_mux;
|
|
|
|
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 3, 0x61);
|
2022-02-18 09:18:11 +01:00
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
/* The rainier expects a TMP275 but a TMP105 is compatible */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
|
|
|
|
0x49);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
|
|
|
|
0x4a);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
|
|
|
|
"pca9546", 0x70);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 4, 0x60);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
|
|
|
|
0x49);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 5, 0x60);
|
|
|
|
create_pca9552(soc, 5, 0x61);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
|
|
|
|
"pca9546", 0x70);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
|
|
|
|
0x4a);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
|
|
|
|
0x4b);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
|
|
|
|
"pca9546", 0x70);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
|
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 7, 0x30);
|
|
|
|
create_pca9552(soc, 7, 0x31);
|
|
|
|
create_pca9552(soc, 7, 0x32);
|
|
|
|
create_pca9552(soc, 7, 0x33);
|
|
|
|
create_pca9552(soc, 7, 0x60);
|
|
|
|
create_pca9552(soc, 7, 0x61);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
|
2021-05-01 10:03:52 +02:00
|
|
|
/* Bus 7: TODO si7021-a20@20 */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
|
|
|
|
0x48);
|
2022-06-30 09:21:13 +02:00
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
|
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
|
|
|
|
0x4a);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
|
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 8, 0x60);
|
|
|
|
create_pca9552(soc, 8, 0x61);
|
2021-05-01 10:03:52 +02:00
|
|
|
/* Bus 8: ucd90320@11 */
|
|
|
|
/* Bus 8: ucd90320@b */
|
|
|
|
/* Bus 8: ucd90320@c */
|
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
|
2021-05-01 10:03:52 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
|
|
|
|
0x48);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
|
|
|
|
0x49);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
|
|
|
|
"pca9546", 0x70);
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
|
|
|
|
at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 11, 0x60);
|
2021-09-20 08:50:59 +02:00
|
|
|
|
|
|
|
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 13, 0x60);
|
2021-09-20 08:50:59 +02:00
|
|
|
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 14, 0x60);
|
2021-09-20 08:50:59 +02:00
|
|
|
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
|
2022-02-18 09:18:13 +01:00
|
|
|
create_pca9552(soc, 15, 0x60);
|
2021-05-01 10:03:52 +02:00
|
|
|
}
|
|
|
|
|
2021-09-20 08:50:59 +02:00
|
|
|
static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
|
|
|
|
I2CBus **channels)
|
|
|
|
{
|
|
|
|
I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
|
|
|
|
for (int i = 0; i < 8; i++) {
|
|
|
|
channels[i] = pca954x_i2c_get_bus(mux, i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#define TYPE_LM75 TYPE_TMP105
|
|
|
|
#define TYPE_TMP75 TYPE_TMP105
|
|
|
|
#define TYPE_TMP422 "tmp422"
|
|
|
|
|
|
|
|
static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
I2CBus *i2c[144] = {};
|
|
|
|
|
|
|
|
for (int i = 0; i < 16; i++) {
|
|
|
|
i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
|
|
|
|
}
|
|
|
|
I2CBus *i2c180 = i2c[2];
|
|
|
|
I2CBus *i2c480 = i2c[8];
|
|
|
|
I2CBus *i2c600 = i2c[11];
|
|
|
|
|
|
|
|
get_pca9548_channels(i2c180, 0x70, &i2c[16]);
|
|
|
|
get_pca9548_channels(i2c480, 0x70, &i2c[24]);
|
|
|
|
/* NOTE: The device tree skips [32, 40) in the alias numbering */
|
|
|
|
get_pca9548_channels(i2c600, 0x77, &i2c[40]);
|
|
|
|
get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
|
|
|
|
get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
|
|
|
|
get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
|
|
|
|
get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
|
|
|
|
for (int i = 0; i < 8; i++) {
|
|
|
|
get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
|
|
|
|
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
/*
|
|
|
|
* EEPROM 24c64 size is 64Kbits or 8 Kbytes
|
|
|
|
* 24c02 size is 2Kbits or 256 bytes
|
|
|
|
*/
|
|
|
|
at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[20], 0x50, 256);
|
|
|
|
at24c_eeprom_init(i2c[22], 0x52, 256);
|
2021-09-20 08:50:59 +02:00
|
|
|
|
|
|
|
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
|
|
|
|
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
|
|
|
|
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
|
|
|
|
i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
|
|
|
|
|
|
|
|
i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
|
2023-03-02 13:57:50 +01:00
|
|
|
at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
|
|
|
|
i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
|
|
|
|
|
|
|
|
i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
|
|
|
|
i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
|
|
|
|
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
|
2023-03-02 13:57:50 +01:00
|
|
|
at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
|
2021-09-20 08:50:59 +02:00
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
|
|
|
|
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
|
2023-03-02 13:57:50 +01:00
|
|
|
at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[28], 0x50, 256);
|
2021-09-20 08:50:59 +02:00
|
|
|
|
|
|
|
for (int i = 0; i < 8; i++) {
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
|
2021-09-20 08:50:59 +02:00
|
|
|
i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
|
|
|
|
i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
|
|
|
|
i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-03-08 09:18:11 +01:00
|
|
|
#define TYPE_TMP421 "tmp421"
|
|
|
|
|
|
|
|
static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
I2CBus *i2c[13] = {};
|
|
|
|
for (int i = 0; i < 13; i++) {
|
|
|
|
if ((i == 8) || (i == 11)) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Bus 0 - 5 all have the same config. */
|
|
|
|
for (int i = 0; i < 6; i++) {
|
|
|
|
/* Missing model: ti,ina230 @ 0x45 */
|
|
|
|
/* Missing model: mps,mp5023 @ 0x40 */
|
|
|
|
i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
|
|
|
|
/* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
|
|
|
|
i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
|
|
|
|
i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
|
|
|
|
/* Missing model: fsc,fusb302 @ 0x22 */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Bus 6 */
|
|
|
|
at24c_eeprom_init(i2c[6], 0x56, 65536);
|
|
|
|
/* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
|
|
|
|
i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
|
|
|
|
|
|
|
|
|
|
|
|
/* Bus 7 */
|
|
|
|
at24c_eeprom_init(i2c[7], 0x54, 65536);
|
|
|
|
|
|
|
|
/* Bus 9 */
|
|
|
|
i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
|
|
|
|
|
|
|
|
/* Bus 10 */
|
|
|
|
i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
|
|
|
|
/* Missing model: ti,hdc1080 @ 0x40 */
|
|
|
|
i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
|
|
|
|
|
|
|
|
/* Bus 12 */
|
|
|
|
/* Missing model: adi,adm1278 @ 0x11 */
|
|
|
|
i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
|
|
|
|
i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
|
|
|
|
i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
|
|
|
|
}
|
|
|
|
|
2022-05-25 10:31:33 +02:00
|
|
|
static void fby35_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
I2CBus *i2c[16];
|
|
|
|
|
|
|
|
for (int i = 0; i < 16; i++) {
|
|
|
|
i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
|
|
|
|
i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
|
|
|
|
/* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
|
|
|
|
i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
|
|
|
|
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
|
|
|
|
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
|
|
|
|
|
2023-02-07 09:02:04 +01:00
|
|
|
at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
|
|
|
|
at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
|
2023-02-07 09:02:05 +01:00
|
|
|
at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
|
|
|
|
fby35_nic_fruid_len);
|
|
|
|
at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
|
|
|
|
fby35_bb_fruid_len);
|
|
|
|
at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
|
|
|
|
fby35_bmc_fruid_len);
|
2022-05-25 10:31:33 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
|
|
|
|
* buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
|
|
|
|
* each.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
|
|
|
|
}
|
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
2022-06-30 09:21:13 +02:00
|
|
|
I2CSlave *therm_mux, *cpuvr_mux;
|
2022-06-30 09:21:13 +02:00
|
|
|
|
|
|
|
/* Create the generic DC-SCM hardware */
|
|
|
|
qcom_dc_scm_bmc_i2c_init(bmc);
|
|
|
|
|
|
|
|
/* Now create the Firework specific hardware */
|
2022-06-30 09:21:13 +02:00
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
/* I2C7 CPUVR MUX */
|
|
|
|
cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
|
|
|
|
"pca9546", 0x70);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
|
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
/* I2C8 Thermal Diodes*/
|
|
|
|
therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
|
|
|
|
"pca9548", 0x70);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
|
|
|
|
i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
|
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
/* I2C9 Fan Controller (MAX31785) */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
|
2022-06-30 09:21:13 +02:00
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
return ASPEED_MACHINE(obj)->mmio_exec;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
|
|
|
ASPEED_MACHINE(obj)->mmio_exec = value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_machine_instance_init(Object *obj)
|
|
|
|
{
|
|
|
|
ASPEED_MACHINE(obj)->mmio_exec = false;
|
|
|
|
}
|
|
|
|
|
2020-09-18 09:04:36 +02:00
|
|
|
static char *aspeed_get_fmc_model(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
return g_strdup(bmc->fmc_model);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
|
|
|
|
g_free(bmc->fmc_model);
|
|
|
|
bmc->fmc_model = g_strdup(value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static char *aspeed_get_spi_model(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
return g_strdup(bmc->spi_model);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(obj);
|
|
|
|
|
|
|
|
g_free(bmc->spi_model);
|
|
|
|
bmc->spi_model = g_strdup(value);
|
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:02 +01:00
|
|
|
static void aspeed_machine_class_props_init(ObjectClass *oc)
|
|
|
|
{
|
|
|
|
object_class_property_add_bool(oc, "execute-in-place",
|
|
|
|
aspeed_get_mmio_exec,
|
qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 17:29:22 +02:00
|
|
|
aspeed_set_mmio_exec);
|
2020-01-30 17:02:02 +01:00
|
|
|
object_class_property_set_description(oc, "execute-in-place",
|
2020-05-05 17:29:15 +02:00
|
|
|
"boot directly from CE0 flash device");
|
2020-09-18 09:04:36 +02:00
|
|
|
|
|
|
|
object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
|
|
|
|
aspeed_set_fmc_model);
|
|
|
|
object_class_property_set_description(oc, "fmc-model",
|
|
|
|
"Change the FMC Flash model");
|
|
|
|
object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
|
|
|
|
aspeed_set_spi_model);
|
|
|
|
object_class_property_set_description(oc, "spi-model",
|
|
|
|
"Change the SPI Flash model");
|
2020-01-30 17:02:02 +01:00
|
|
|
}
|
|
|
|
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
static int aspeed_soc_num_cpus(const char *soc_name)
|
|
|
|
{
|
|
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
|
|
|
|
return sc->num_cpus;
|
|
|
|
}
|
|
|
|
|
2018-09-25 15:02:33 +02:00
|
|
|
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
|
2018-06-08 14:15:32 +02:00
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
2018-06-08 14:15:32 +02:00
|
|
|
|
2018-09-25 15:02:33 +02:00
|
|
|
mc->init = aspeed_machine_init;
|
2018-06-08 14:15:32 +02:00
|
|
|
mc->no_floppy = 1;
|
|
|
|
mc->no_cdrom = 1;
|
|
|
|
mc->no_parallel = 1;
|
2020-02-19 17:08:44 +01:00
|
|
|
mc->default_ram_id = "ram";
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC0_ON;
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->uart_default = ASPEED_DEV_UART5;
|
2020-01-30 17:02:02 +01:00
|
|
|
|
|
|
|
aspeed_machine_class_props_init(oc);
|
2018-06-08 14:15:32 +02:00
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
|
|
|
|
amc->soc_name = "ast2400-a1";
|
|
|
|
amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q256a";
|
2022-10-24 11:20:16 +02:00
|
|
|
amc->spi_model = "mx25l25635f";
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->i2c_init = palmetto_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 256 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
|
|
|
|
amc->soc_name = "ast2400-a1";
|
|
|
|
amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q256a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->i2c_init = quanta_q71l_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 128 * MiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
}
|
|
|
|
|
2020-09-01 14:21:50 +02:00
|
|
|
static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
|
|
|
|
amc->soc_name = "ast2400-a1";
|
|
|
|
amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "mx25l25635e";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
|
|
|
|
amc->i2c_init = palmetto_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 256 * MiB;
|
|
|
|
}
|
|
|
|
|
2023-02-07 09:02:04 +01:00
|
|
|
static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "mx25l25635e";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
|
|
|
|
amc->i2c_init = palmetto_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Aspeed AST2500 EVB (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
|
2022-05-02 17:03:04 +02:00
|
|
|
amc->fmc_model = "mx25l25635e";
|
2022-10-24 11:20:16 +02:00
|
|
|
amc->spi_model = "mx25l25635f";
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->num_cs = 1;
|
|
|
|
amc->i2c_init = ast2500_evb_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = 0;
|
|
|
|
amc->fmc_model = "n25q256a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = yosemitev2_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q256a";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = romulus_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2018-09-25 15:02:33 +02:00
|
|
|
};
|
|
|
|
|
2023-03-02 13:57:50 +01:00
|
|
|
static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Facebook Tiogapass BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = 0;
|
|
|
|
amc->fmc_model = "n25q256a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = tiogapass_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2020-05-06 20:32:19 +02:00
|
|
|
static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OCP SonoraPass BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = sonorapass_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2020-05-06 20:32:19 +02:00
|
|
|
};
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
|
2022-10-24 11:20:16 +02:00
|
|
|
amc->fmc_model = "mx25l25635f";
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->i2c_init = witherspoon_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
2021-05-27 11:51:52 +02:00
|
|
|
mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->soc_name = "ast2600-a3";
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
|
2022-05-02 17:03:04 +02:00
|
|
|
amc->fmc_model = "mx66u51235f";
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->spi_model = "mx66u51235f";
|
|
|
|
amc->num_cs = 1;
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
|
|
|
|
ASPEED_MAC3_ON;
|
2019-11-19 15:12:07 +01:00
|
|
|
amc->i2c_init = ast2600_evb_i2c_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
|
|
|
|
2019-11-19 15:12:08 +01:00
|
|
|
static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
2021-05-27 11:51:52 +02:00
|
|
|
mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->soc_name = "ast2600-a3";
|
2019-11-19 15:12:08 +01:00
|
|
|
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
arm/aspeed: Rework NIC attachment
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
2020-06-09 14:23:20 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC2_ON;
|
2019-11-19 15:12:08 +01:00
|
|
|
amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
arm/aspeed: Compute the number of CPUs from the SoC definition
Commit ece09beec457 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
2020-06-09 14:23:19 +02:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
2019-11-19 15:12:08 +01:00
|
|
|
};
|
|
|
|
|
2020-12-10 12:11:03 +01:00
|
|
|
static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Bytedance G220A BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = G220A_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q512a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 2;
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
|
2020-12-10 12:11:03 +01:00
|
|
|
amc->i2c_init = g220a_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 1024 * MiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2021-10-22 09:52:16 +02:00
|
|
|
static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
|
|
|
|
amc->soc_name = "ast2500-a1";
|
|
|
|
amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
|
|
|
|
amc->fmc_model = "n25q512a";
|
|
|
|
amc->spi_model = "mx25l25635e";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
|
|
|
|
amc->i2c_init = fp5280g2_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 512 * MiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2021-05-01 10:03:52 +02:00
|
|
|
static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
2021-05-27 11:51:52 +02:00
|
|
|
mc->desc = "IBM Rainier BMC (Cortex-A7)";
|
2021-09-20 08:50:59 +02:00
|
|
|
amc->soc_name = "ast2600-a3";
|
2021-05-01 10:03:52 +02:00
|
|
|
amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
|
|
|
|
amc->i2c_init = rainier_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2021-09-20 08:50:59 +02:00
|
|
|
/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
|
|
|
|
#if HOST_LONG_BITS == 32
|
|
|
|
#define FUJI_BMC_RAM_SIZE (1 * GiB)
|
|
|
|
#else
|
|
|
|
#define FUJI_BMC_RAM_SIZE (2 * GiB)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Facebook Fuji BMC (Cortex-A7)";
|
|
|
|
amc->soc_name = "ast2600-a3";
|
|
|
|
amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->spi_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC3_ON;
|
|
|
|
amc->i2c_init = fuji_bmc_i2c_init;
|
|
|
|
amc->uart_default = ASPEED_DEV_UART1;
|
|
|
|
mc->default_ram_size = FUJI_BMC_RAM_SIZE;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2022-10-24 11:20:15 +02:00
|
|
|
/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
|
|
|
|
#if HOST_LONG_BITS == 32
|
|
|
|
#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
|
|
|
|
#else
|
|
|
|
#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
|
|
|
|
#endif
|
|
|
|
|
2022-03-08 09:18:11 +01:00
|
|
|
static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
|
|
|
|
amc->soc_name = "ast2600-a3";
|
|
|
|
amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "w25q01jvq";
|
|
|
|
amc->spi_model = NULL;
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC2_ON;
|
|
|
|
amc->i2c_init = bletchley_bmc_i2c_init;
|
2022-10-24 11:20:15 +02:00
|
|
|
mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
|
2022-03-08 09:18:11 +01:00
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
}
|
|
|
|
|
2022-10-25 02:43:17 +02:00
|
|
|
static void fby35_reset(MachineState *state, ShutdownCause reason)
|
2022-05-25 10:31:33 +02:00
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(state);
|
|
|
|
AspeedGPIOState *gpio = &bmc->soc.gpio;
|
|
|
|
|
2022-10-25 02:43:17 +02:00
|
|
|
qemu_devices_reset(reason);
|
2022-05-25 10:31:33 +02:00
|
|
|
|
2022-07-14 16:24:38 +02:00
|
|
|
/* Board ID: 7 (Class-1, 4 slots) */
|
2022-05-25 10:31:33 +02:00
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
|
2022-07-14 16:24:38 +02:00
|
|
|
|
|
|
|
/* Slot presence pins, inverse polarity. (False means present) */
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
|
|
|
|
|
|
|
|
/* Slot 12v power pins, normal polarity. (True means powered-on) */
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
|
2022-05-25 10:31:33 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Facebook fby35 BMC (Cortex-A7)";
|
|
|
|
mc->reset = fby35_reset;
|
|
|
|
amc->fmc_model = "mx66l1g45g";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC3_ON;
|
|
|
|
amc->i2c_init = fby35_i2c_init;
|
|
|
|
/* FIXME: Replace this macro with something more general */
|
|
|
|
mc->default_ram_size = FUJI_BMC_RAM_SIZE;
|
|
|
|
}
|
|
|
|
|
2022-05-02 17:03:03 +02:00
|
|
|
#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
|
|
|
|
/* Main SYSCLK frequency in Hz (200MHz) */
|
|
|
|
#define SYSCLK_FRQ 200000000ULL
|
|
|
|
|
|
|
|
static void aspeed_minibmc_machine_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
AspeedMachineState *bmc = ASPEED_MACHINE(machine);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
|
|
|
|
Clock *sysclk;
|
|
|
|
|
|
|
|
sysclk = clock_new(OBJECT(machine), "SYSCLK");
|
|
|
|
clock_set_hz(sysclk, SYSCLK_FRQ);
|
|
|
|
|
|
|
|
object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
|
|
|
|
qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
|
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
object_property_set_link(OBJECT(&bmc->soc), "memory",
|
|
|
|
OBJECT(get_system_memory()), &error_abort);
|
aspeed: Refactor UART init for multi-SoC machines
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allow multi-SoC
boards to completely change the wiring of serial devices from the
command line to specific SoC UART's.
This also removes the uart-default property from the SoC, since the SoC
doesn't need to know what UART is the "default" on the machine anymore.
I tested this using the images and commands from the previous
refactoring, and another test image for the ast1030:
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Fuji uses UART1:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
ast2600-evb uses uart-default=UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
Wedge100 uses UART3:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
AST1030 EVB uses UART5:
qemu-system-arm -machine ast1030-evb \
-kernel Y35BCL.elf -nographic
Fixes: 6827ff20b2975 ("hw: aspeed: Init all UART's with serial devices")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-07-14 16:24:38 +02:00
|
|
|
connect_serial_hds_to_uarts(bmc);
|
2022-05-02 17:03:03 +02:00
|
|
|
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
|
|
|
|
|
|
|
|
aspeed_board_init_flashes(&bmc->soc.fmc,
|
|
|
|
bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
|
|
|
|
amc->num_cs,
|
|
|
|
0);
|
|
|
|
|
|
|
|
aspeed_board_init_flashes(&bmc->soc.spi[0],
|
|
|
|
bmc->spi_model ? bmc->spi_model : amc->spi_model,
|
|
|
|
amc->num_cs, amc->num_cs);
|
|
|
|
|
|
|
|
aspeed_board_init_flashes(&bmc->soc.spi[1],
|
|
|
|
bmc->spi_model ? bmc->spi_model : amc->spi_model,
|
|
|
|
amc->num_cs, (amc->num_cs * 2));
|
|
|
|
|
|
|
|
if (amc->i2c_init) {
|
|
|
|
amc->i2c_init(bmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
armv7m_load_kernel(ARM_CPU(first_cpu),
|
|
|
|
machine->kernel_filename,
|
2022-08-23 18:04:17 +02:00
|
|
|
0,
|
2022-05-02 17:03:03 +02:00
|
|
|
AST1030_INTERNAL_FLASH_SIZE);
|
|
|
|
}
|
|
|
|
|
2022-06-13 14:05:48 +02:00
|
|
|
static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
|
|
|
|
{
|
|
|
|
AspeedSoCState *soc = &bmc->soc;
|
|
|
|
|
|
|
|
/* U10 24C08 connects to SDA/SCL Groupt 1 by default */
|
|
|
|
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
|
|
|
|
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
|
|
|
|
|
|
|
|
/* U11 LM75 connects to SDA/SCL Group 2 by default */
|
|
|
|
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
|
|
|
|
}
|
|
|
|
|
2022-05-02 17:03:03 +02:00
|
|
|
static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
|
|
|
|
amc->soc_name = "ast1030-a1";
|
|
|
|
amc->hw_strap1 = 0;
|
|
|
|
amc->hw_strap2 = 0;
|
|
|
|
mc->init = aspeed_minibmc_machine_init;
|
2022-06-13 14:05:48 +02:00
|
|
|
amc->i2c_init = ast1030_evb_i2c_init;
|
2022-05-02 17:03:03 +02:00
|
|
|
mc->default_ram_size = 0;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
|
|
|
|
amc->fmc_model = "sst25vf032b";
|
|
|
|
amc->spi_model = "sst25vf032b";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = 0;
|
|
|
|
}
|
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
|
|
|
|
amc->soc_name = "ast2600-a3";
|
|
|
|
amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "n25q512a";
|
|
|
|
amc->spi_model = "n25q512a";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
|
|
|
|
amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2022-06-30 09:21:13 +02:00
|
|
|
static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
|
|
|
|
amc->soc_name = "ast2600-a3";
|
|
|
|
amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
|
|
|
|
amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
|
|
|
|
amc->fmc_model = "n25q512a";
|
|
|
|
amc->spi_model = "n25q512a";
|
|
|
|
amc->num_cs = 2;
|
|
|
|
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
|
|
|
|
amc->i2c_init = qcom_dc_scm_firework_i2c_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
|
|
|
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
|
|
|
aspeed_soc_num_cpus(amc->soc_name);
|
|
|
|
};
|
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
static const TypeInfo aspeed_machine_types[] = {
|
2018-09-25 15:02:33 +02:00
|
|
|
{
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("palmetto-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_palmetto_class_init,
|
2020-09-01 14:21:50 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
|
2023-02-07 09:02:04 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
|
2018-09-25 15:02:33 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("ast2500-evb"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_ast2500_evb_class_init,
|
2018-09-25 15:02:33 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("romulus-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_romulus_class_init,
|
2020-05-06 20:32:19 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("sonorapass-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_sonorapass_class_init,
|
2018-09-25 15:02:33 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_witherspoon_class_init,
|
2019-10-23 15:04:55 +02:00
|
|
|
}, {
|
2019-11-19 15:12:07 +01:00
|
|
|
.name = MACHINE_TYPE_NAME("ast2600-evb"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_ast2600_evb_class_init,
|
2023-03-02 13:57:50 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_yosemitev2_class_init,
|
2019-11-19 15:12:08 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("tacoma-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_tacoma_class_init,
|
2023-03-02 13:57:50 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("tiogapass-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_tiogapass_class_init,
|
2020-12-10 12:11:03 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("g220a-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_g220a_class_init,
|
2022-06-30 09:21:13 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
|
2022-06-30 09:21:13 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_qcom_firework_class_init,
|
2021-10-22 09:52:16 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_fp5280g2_class_init,
|
2021-05-01 10:03:52 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_quanta_q71l_class_init,
|
2021-05-01 10:03:52 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("rainier-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_rainier_class_init,
|
2021-09-20 08:50:59 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("fuji-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_fuji_class_init,
|
2022-03-08 09:18:11 +01:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("bletchley-bmc"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_machine_bletchley_class_init,
|
2022-05-25 10:31:33 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("fby35-bmc"),
|
|
|
|
.parent = MACHINE_TYPE_NAME("ast2600-evb"),
|
|
|
|
.class_init = aspeed_machine_fby35_class_init,
|
2022-05-02 17:03:03 +02:00
|
|
|
}, {
|
|
|
|
.name = MACHINE_TYPE_NAME("ast1030-evb"),
|
|
|
|
.parent = TYPE_ASPEED_MACHINE,
|
|
|
|
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
|
2019-11-19 15:12:07 +01:00
|
|
|
}, {
|
|
|
|
.name = TYPE_ASPEED_MACHINE,
|
|
|
|
.parent = TYPE_MACHINE,
|
2020-06-23 09:21:32 +02:00
|
|
|
.instance_size = sizeof(AspeedMachineState),
|
2020-01-30 17:02:02 +01:00
|
|
|
.instance_init = aspeed_machine_instance_init,
|
2019-11-19 15:12:07 +01:00
|
|
|
.class_size = sizeof(AspeedMachineClass),
|
|
|
|
.class_init = aspeed_machine_class_init,
|
|
|
|
.abstract = true,
|
2018-09-25 15:02:33 +02:00
|
|
|
}
|
2019-11-19 15:12:07 +01:00
|
|
|
};
|
2016-09-22 19:13:05 +02:00
|
|
|
|
2019-11-19 15:12:07 +01:00
|
|
|
DEFINE_TYPES(aspeed_machine_types)
|