2012-02-14 01:16:17 +01:00
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/*
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* QEMU UniCore32 CPU
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*
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2012-08-10 08:42:23 +02:00
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* Copyright (c) 2010-2012 Guan Xuetao
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2012-02-14 01:16:17 +01:00
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Contributions from 2012-04-01 on are considered under GPL version 2,
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* or (at your option) any later version.
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*/
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2016-01-26 19:17:01 +01:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2012-05-03 06:43:49 +02:00
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#include "cpu.h"
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2012-02-14 01:16:17 +01:00
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#include "qemu-common.h"
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2013-01-20 11:43:30 +01:00
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#include "migration/vmstate.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2018-01-19 19:24:22 +01:00
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#include "fpu/softfloat.h"
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2012-02-14 01:16:17 +01:00
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2013-06-28 19:41:07 +02:00
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static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(cs);
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cpu->env.regs[31] = value;
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}
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2013-08-25 18:53:55 +02:00
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static bool uc32_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
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}
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2012-03-29 18:03:18 +02:00
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static inline void set_feature(CPUUniCore32State *env, int feature)
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{
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env->features |= feature;
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}
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2012-02-14 01:16:17 +01:00
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/* CPU models */
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2013-01-23 12:07:17 +01:00
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static ObjectClass *uc32_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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2013-01-27 23:25:25 +01:00
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char *typename;
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2013-01-23 12:07:17 +01:00
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2017-10-05 15:51:01 +02:00
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typename = g_strdup_printf(UNICORE32_CPU_TYPE_NAME("%s"), cpu_model);
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2013-01-27 23:25:25 +01:00
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oc = object_class_by_name(typename);
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g_free(typename);
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2013-01-23 12:41:38 +01:00
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_UNICORE32_CPU) ||
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object_class_is_abstract(oc))) {
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2013-01-23 12:07:17 +01:00
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oc = NULL;
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}
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return oc;
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}
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2012-02-14 01:16:17 +01:00
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static void unicore_ii_cpu_initfn(Object *obj)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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2012-08-10 08:42:23 +02:00
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env->cp0.c0_cpuid = 0x4d000863;
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env->cp0.c0_cachetype = 0x0d152152;
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env->cp0.c1_sys = 0x2000;
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env->cp0.c2_base = 0x0;
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env->cp0.c3_faultstatus = 0x0;
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env->cp0.c4_faultaddr = 0x0;
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env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
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2012-03-29 18:03:18 +02:00
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set_feature(env, UC32_HWCAP_CMOV);
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set_feature(env, UC32_HWCAP_UCF64);
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softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Tested-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[leon.alrae@imgtec.com:
* cherry-picked 2 chunks from patch #2 to fix compilation warnings]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:28 +02:00
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set_snan_bit_is_one(1, &env->ucf64.fp_status);
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2012-02-14 01:16:17 +01:00
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}
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static void uc32_any_cpu_initfn(Object *obj)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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env->cp0.c0_cpuid = 0xffffffff;
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2012-08-10 08:42:23 +02:00
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env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
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2012-03-29 18:03:18 +02:00
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set_feature(env, UC32_HWCAP_CMOV);
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set_feature(env, UC32_HWCAP_UCF64);
|
softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Tested-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[leon.alrae@imgtec.com:
* cherry-picked 2 chunks from patch #2 to fix compilation warnings]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:28 +02:00
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set_snan_bit_is_one(1, &env->ucf64.fp_status);
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2012-02-14 01:16:17 +01:00
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}
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2013-01-05 14:38:30 +01:00
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static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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2016-10-20 13:26:03 +02:00
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CPUState *cs = CPU(dev);
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2013-01-05 14:38:30 +01:00
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UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
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2016-10-20 13:26:03 +02:00
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Error *local_err = NULL;
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2013-01-05 14:38:30 +01:00
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2016-10-20 13:26:03 +02:00
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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2013-07-27 02:53:25 +02:00
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2013-01-05 14:38:30 +01:00
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ucc->parent_realize(dev, errp);
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}
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2012-02-14 01:16:17 +01:00
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static void uc32_cpu_initfn(Object *obj)
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{
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2013-01-17 12:13:41 +01:00
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CPUState *cs = CPU(obj);
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2012-02-14 01:16:17 +01:00
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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2013-01-17 12:13:41 +01:00
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cs->env_ptr = env;
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2012-02-14 01:16:17 +01:00
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2012-08-10 08:42:23 +02:00
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#ifdef CONFIG_USER_ONLY
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2012-02-14 01:16:17 +01:00
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env->uncached_asr = ASR_MODE_USER;
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env->regs[31] = 0;
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2012-08-10 08:42:23 +02:00
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#else
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env->uncached_asr = ASR_MODE_PRIV;
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env->regs[31] = 0x03000000;
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#endif
|
2012-02-14 01:16:17 +01:00
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|
2016-11-14 15:17:28 +01:00
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tlb_flush(cs);
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2012-02-14 01:16:17 +01:00
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}
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|
2013-01-20 11:43:30 +01:00
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static const VMStateDescription vmstate_uc32_cpu = {
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|
.name = "cpu",
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.unmigratable = 1,
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};
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|
|
|
2013-01-23 12:07:17 +01:00
|
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static void uc32_cpu_class_init(ObjectClass *oc, void *data)
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|
|
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{
|
2013-01-20 11:43:30 +01:00
|
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DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-01-23 12:07:17 +01:00
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CPUClass *cc = CPU_CLASS(oc);
|
2013-01-05 14:38:30 +01:00
|
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|
UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
|
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|
2018-01-14 03:04:12 +01:00
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device_class_set_parent_realize(dc, uc32_cpu_realizefn,
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&ucc->parent_realize);
|
2013-01-23 12:07:17 +01:00
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cc->class_by_name = uc32_cpu_class_by_name;
|
2013-08-25 18:53:55 +02:00
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cc->has_work = uc32_cpu_has_work;
|
2013-02-02 10:57:51 +01:00
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cc->do_interrupt = uc32_cpu_do_interrupt;
|
2014-09-13 18:45:24 +02:00
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cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt;
|
2013-05-27 01:33:50 +02:00
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cc->dump_state = uc32_cpu_dump_state;
|
2013-06-28 19:41:07 +02:00
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cc->set_pc = uc32_cpu_set_pc;
|
2013-08-26 03:01:33 +02:00
|
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault;
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#else
|
2013-06-29 18:55:54 +02:00
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cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
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#endif
|
2017-10-16 04:02:42 +02:00
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cc->tcg_initialize = uc32_translate_init;
|
2013-01-20 11:43:30 +01:00
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dc->vmsd = &vmstate_uc32_cpu;
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2013-01-23 12:07:17 +01:00
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|
}
|
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|
2017-10-05 15:51:01 +02:00
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|
|
#define DEFINE_UNICORE32_CPU_TYPE(cpu_model, initfn) \
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{ \
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.parent = TYPE_UNICORE32_CPU, \
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.instance_init = initfn, \
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.name = UNICORE32_CPU_TYPE_NAME(cpu_model), \
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}
|
2012-02-14 01:16:17 +01:00
|
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|
2017-10-05 15:51:01 +02:00
|
|
|
static const TypeInfo uc32_cpu_type_infos[] = {
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|
|
{
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.name = TYPE_UNICORE32_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(UniCore32CPU),
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|
|
.instance_init = uc32_cpu_initfn,
|
|
|
|
.abstract = true,
|
|
|
|
.class_size = sizeof(UniCore32CPUClass),
|
|
|
|
.class_init = uc32_cpu_class_init,
|
|
|
|
},
|
|
|
|
DEFINE_UNICORE32_CPU_TYPE("UniCore-II", unicore_ii_cpu_initfn),
|
|
|
|
DEFINE_UNICORE32_CPU_TYPE("any", uc32_any_cpu_initfn),
|
2012-02-14 01:16:17 +01:00
|
|
|
};
|
|
|
|
|
2017-10-05 15:51:01 +02:00
|
|
|
DEFINE_TYPES(uc32_cpu_type_infos)
|