target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# LoongArch instruction decode definitions.
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#
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# Copyright (c) 2021 Loongson Technology Corporation Limited
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#
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#
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# Fields
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#
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2022-06-06 14:42:57 +02:00
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%i14s2 10:s14 !function=shl_2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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%sa2p1 15:2 !function=plus_1
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#
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# Argument sets
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#
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2022-06-06 14:42:57 +02:00
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&i imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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&r_i rd imm
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2022-06-06 14:42:56 +02:00
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&rr rd rj
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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&rrr rd rj rk
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&rr_i rd rj imm
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2022-06-06 14:42:57 +02:00
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&hint_r_i hint rj imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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&rrr_sa rd rj rk sa
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2022-06-06 14:42:56 +02:00
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&rr_ms_ls rd rj ms ls
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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#
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# Formats
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#
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2022-06-06 14:42:57 +02:00
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@i15 .... ........ ..... imm:15 &i
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2022-06-06 14:42:56 +02:00
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@rr .... ........ ..... ..... rj:5 rd:5 &rr
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
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@r_i20 .... ... imm:s20 rd:5 &r_i
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target/loongarch: Add fixed point shift instruction translation
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:55 +02:00
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@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
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@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
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@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
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2022-06-06 14:42:57 +02:00
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@rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
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2022-06-06 14:42:57 +02:00
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@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
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2022-06-06 14:42:56 +02:00
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@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
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@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa
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@rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls
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@rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:54 +02:00
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#
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# Fixed point arithmetic operation instruction
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#
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add_w 0000 00000001 00000 ..... ..... ..... @rrr
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add_d 0000 00000001 00001 ..... ..... ..... @rrr
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sub_w 0000 00000001 00010 ..... ..... ..... @rrr
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sub_d 0000 00000001 00011 ..... ..... ..... @rrr
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slt 0000 00000001 00100 ..... ..... ..... @rrr
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sltu 0000 00000001 00101 ..... ..... ..... @rrr
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slti 0000 001000 ............ ..... ..... @rr_i12
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sltui 0000 001001 ............ ..... ..... @rr_i12
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nor 0000 00000001 01000 ..... ..... ..... @rrr
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and 0000 00000001 01001 ..... ..... ..... @rrr
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or 0000 00000001 01010 ..... ..... ..... @rrr
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xor 0000 00000001 01011 ..... ..... ..... @rrr
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orn 0000 00000001 01100 ..... ..... ..... @rrr
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andn 0000 00000001 01101 ..... ..... ..... @rrr
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mul_w 0000 00000001 11000 ..... ..... ..... @rrr
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mulh_w 0000 00000001 11001 ..... ..... ..... @rrr
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mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr
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mul_d 0000 00000001 11011 ..... ..... ..... @rrr
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mulh_d 0000 00000001 11100 ..... ..... ..... @rrr
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mulh_du 0000 00000001 11101 ..... ..... ..... @rrr
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mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr
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mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr
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div_w 0000 00000010 00000 ..... ..... ..... @rrr
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mod_w 0000 00000010 00001 ..... ..... ..... @rrr
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div_wu 0000 00000010 00010 ..... ..... ..... @rrr
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mod_wu 0000 00000010 00011 ..... ..... ..... @rrr
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div_d 0000 00000010 00100 ..... ..... ..... @rrr
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mod_d 0000 00000010 00101 ..... ..... ..... @rrr
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div_du 0000 00000010 00110 ..... ..... ..... @rrr
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mod_du 0000 00000010 00111 ..... ..... ..... @rrr
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alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1
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alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1
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alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1
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lu12i_w 0001 010 .................... ..... @r_i20
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lu32i_d 0001 011 .................... ..... @r_i20
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lu52i_d 0000 001100 ............ ..... ..... @rr_i12
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pcaddi 0001 100 .................... ..... @r_i20
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pcalau12i 0001 101 .................... ..... @r_i20
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pcaddu12i 0001 110 .................... ..... @r_i20
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pcaddu18i 0001 111 .................... ..... @r_i20
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addi_w 0000 001010 ............ ..... ..... @rr_i12
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addi_d 0000 001011 ............ ..... ..... @rr_i12
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addu16i_d 0001 00 ................ ..... ..... @rr_i16
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andi 0000 001101 ............ ..... ..... @rr_ui12
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ori 0000 001110 ............ ..... ..... @rr_ui12
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xori 0000 001111 ............ ..... ..... @rr_ui12
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target/loongarch: Add fixed point shift instruction translation
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 14:42:55 +02:00
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#
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# Fixed point shift operation instruction
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#
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sll_w 0000 00000001 01110 ..... ..... ..... @rrr
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srl_w 0000 00000001 01111 ..... ..... ..... @rrr
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sra_w 0000 00000001 10000 ..... ..... ..... @rrr
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sll_d 0000 00000001 10001 ..... ..... ..... @rrr
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srl_d 0000 00000001 10010 ..... ..... ..... @rrr
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sra_d 0000 00000001 10011 ..... ..... ..... @rrr
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rotr_w 0000 00000001 10110 ..... ..... ..... @rrr
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rotr_d 0000 00000001 10111 ..... ..... ..... @rrr
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slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5
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slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6
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srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5
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srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6
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srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5
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srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6
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rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5
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rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6
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2022-06-06 14:42:56 +02:00
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#
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# Fixed point bit operation instruction
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ext_w_h 0000 00000000 00000 10110 ..... ..... @rr
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ext_w_b 0000 00000000 00000 10111 ..... ..... @rr
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clo_w 0000 00000000 00000 00100 ..... ..... @rr
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clz_w 0000 00000000 00000 00101 ..... ..... @rr
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cto_w 0000 00000000 00000 00110 ..... ..... @rr
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ctz_w 0000 00000000 00000 00111 ..... ..... @rr
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clo_d 0000 00000000 00000 01000 ..... ..... @rr
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clz_d 0000 00000000 00000 01001 ..... ..... @rr
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cto_d 0000 00000000 00000 01010 ..... ..... @rr
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ctz_d 0000 00000000 00000 01011 ..... ..... @rr
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revb_2h 0000 00000000 00000 01100 ..... ..... @rr
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revb_4h 0000 00000000 00000 01101 ..... ..... @rr
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revb_2w 0000 00000000 00000 01110 ..... ..... @rr
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revb_d 0000 00000000 00000 01111 ..... ..... @rr
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revh_2w 0000 00000000 00000 10000 ..... ..... @rr
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revh_d 0000 00000000 00000 10001 ..... ..... @rr
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bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr
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bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr
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bitrev_w 0000 00000000 00000 10100 ..... ..... @rr
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bitrev_d 0000 00000000 00000 10101 ..... ..... @rr
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bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2
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bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3
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maskeqz 0000 00000001 00110 ..... ..... ..... @rrr
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masknez 0000 00000001 00111 ..... ..... ..... @rrr
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bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw
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bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw
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bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd
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bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd
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2022-06-06 14:42:57 +02:00
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#
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# Fixed point load/store instruction
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ld_b 0010 100000 ............ ..... ..... @rr_i12
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ld_h 0010 100001 ............ ..... ..... @rr_i12
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ld_w 0010 100010 ............ ..... ..... @rr_i12
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ld_d 0010 100011 ............ ..... ..... @rr_i12
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st_b 0010 100100 ............ ..... ..... @rr_i12
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st_h 0010 100101 ............ ..... ..... @rr_i12
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st_w 0010 100110 ............ ..... ..... @rr_i12
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st_d 0010 100111 ............ ..... ..... @rr_i12
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ld_bu 0010 101000 ............ ..... ..... @rr_i12
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ld_hu 0010 101001 ............ ..... ..... @rr_i12
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ld_wu 0010 101010 ............ ..... ..... @rr_i12
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ldx_b 0011 10000000 00000 ..... ..... ..... @rrr
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ldx_h 0011 10000000 01000 ..... ..... ..... @rrr
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ldx_w 0011 10000000 10000 ..... ..... ..... @rrr
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ldx_d 0011 10000000 11000 ..... ..... ..... @rrr
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stx_b 0011 10000001 00000 ..... ..... ..... @rrr
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stx_h 0011 10000001 01000 ..... ..... ..... @rrr
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stx_w 0011 10000001 10000 ..... ..... ..... @rrr
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stx_d 0011 10000001 11000 ..... ..... ..... @rrr
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ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr
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ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr
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ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr
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preld 0010 101011 ............ ..... ..... @hint_r_i12
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dbar 0011 10000111 00100 ............... @i15
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ibar 0011 10000111 00101 ............... @i15
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ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2
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stptr_w 0010 0101 .............. ..... ..... @rr_i14s2
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ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2
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stptr_d 0010 0111 .............. ..... ..... @rr_i14s2
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ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr
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ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr
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ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr
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ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr
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ldle_b 0011 10000111 10100 ..... ..... ..... @rrr
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ldle_h 0011 10000111 10101 ..... ..... ..... @rrr
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ldle_w 0011 10000111 10110 ..... ..... ..... @rrr
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ldle_d 0011 10000111 10111 ..... ..... ..... @rrr
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stgt_b 0011 10000111 11000 ..... ..... ..... @rrr
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stgt_h 0011 10000111 11001 ..... ..... ..... @rrr
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stgt_w 0011 10000111 11010 ..... ..... ..... @rrr
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stgt_d 0011 10000111 11011 ..... ..... ..... @rrr
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stle_b 0011 10000111 11100 ..... ..... ..... @rrr
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stle_h 0011 10000111 11101 ..... ..... ..... @rrr
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stle_w 0011 10000111 11110 ..... ..... ..... @rrr
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stle_d 0011 10000111 11111 ..... ..... ..... @rrr
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