qemu-e2k/target/ppc/arch_dump.c

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/*
* writing ELF notes for ppc{64,} arch
*
*
* Copyright IBM, Corp. 2013
*
* Authors:
* Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "elf.h"
#include "sysemu/dump.h"
#include "sysemu/kvm.h"
#ifdef TARGET_PPC64
#define ELFCLASS ELFCLASS64
#define cpu_to_dump_reg cpu_to_dump64
typedef uint64_t reg_t;
typedef Elf64_Nhdr Elf_Nhdr;
#else
#define ELFCLASS ELFCLASS32
#define cpu_to_dump_reg cpu_to_dump32
typedef uint32_t reg_t;
typedef Elf32_Nhdr Elf_Nhdr;
#endif /* TARGET_PPC64 */
struct PPCUserRegStruct {
reg_t gpr[32];
reg_t nip;
reg_t msr;
reg_t orig_gpr3;
reg_t ctr;
reg_t link;
reg_t xer;
reg_t ccr;
reg_t softe;
reg_t trap;
reg_t dar;
reg_t dsisr;
reg_t result;
} QEMU_PACKED;
struct PPCElfPrstatus {
char pad1[112];
struct PPCUserRegStruct pr_reg;
char pad2[40];
} QEMU_PACKED;
struct PPCElfFpregset {
uint64_t fpr[32];
reg_t fpscr;
} QEMU_PACKED;
struct PPCElfVmxregset {
ppc_avr_t avr[32];
ppc_avr_t vscr;
union {
ppc_avr_t unused;
uint32_t value;
} vrsave;
} QEMU_PACKED;
struct PPCElfVsxregset {
uint64_t vsr[32];
} QEMU_PACKED;
struct PPCElfSperegset {
uint32_t evr[32];
uint64_t spe_acc;
uint32_t spe_fscr;
} QEMU_PACKED;
typedef struct noteStruct {
Elf_Nhdr hdr;
char name[5];
char pad3[3];
union {
struct PPCElfPrstatus prstatus;
struct PPCElfFpregset fpregset;
struct PPCElfVmxregset vmxregset;
struct PPCElfVsxregset vsxregset;
struct PPCElfSperegset speregset;
} contents;
} QEMU_PACKED Note;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
typedef struct NoteFuncArg {
Note note;
DumpState *state;
} NoteFuncArg;
static void ppc_write_elf_prstatus(NoteFuncArg *arg, PowerPCCPU *cpu)
{
int i;
reg_t cr;
struct PPCElfPrstatus *prstatus;
struct PPCUserRegStruct *reg;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
Note *note = &arg->note;
DumpState *s = arg->state;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
note->hdr.n_type = cpu_to_dump32(s, NT_PRSTATUS);
prstatus = &note->contents.prstatus;
memset(prstatus, 0, sizeof(*prstatus));
reg = &prstatus->pr_reg;
for (i = 0; i < 32; i++) {
reg->gpr[i] = cpu_to_dump_reg(s, cpu->env.gpr[i]);
}
reg->nip = cpu_to_dump_reg(s, cpu->env.nip);
reg->msr = cpu_to_dump_reg(s, cpu->env.msr);
reg->ctr = cpu_to_dump_reg(s, cpu->env.ctr);
reg->link = cpu_to_dump_reg(s, cpu->env.lr);
reg->xer = cpu_to_dump_reg(s, cpu_read_xer(&cpu->env));
cr = 0;
for (i = 0; i < 8; i++) {
cr |= (cpu->env.crf[i] & 15) << (4 * (7 - i));
}
reg->ccr = cpu_to_dump_reg(s, cr);
}
static void ppc_write_elf_fpregset(NoteFuncArg *arg, PowerPCCPU *cpu)
{
int i;
struct PPCElfFpregset *fpregset;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
Note *note = &arg->note;
DumpState *s = arg->state;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
note->hdr.n_type = cpu_to_dump32(s, NT_PRFPREG);
fpregset = &note->contents.fpregset;
memset(fpregset, 0, sizeof(*fpregset));
for (i = 0; i < 32; i++) {
target/ppc: move FP and VMX registers into aligned vsr register array The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vector operations, recreate the same layout using an aligned version of the existing vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. This also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-02 10:14:22 +01:00
uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
fpregset->fpr[i] = cpu_to_dump64(s, *fpr);
}
fpregset->fpscr = cpu_to_dump_reg(s, cpu->env.fpscr);
}
static void ppc_write_elf_vmxregset(NoteFuncArg *arg, PowerPCCPU *cpu)
{
int i;
struct PPCElfVmxregset *vmxregset;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
Note *note = &arg->note;
DumpState *s = arg->state;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
note->hdr.n_type = cpu_to_dump32(s, NT_PPC_VMX);
vmxregset = &note->contents.vmxregset;
memset(vmxregset, 0, sizeof(*vmxregset));
for (i = 0; i < 32; i++) {
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
bool needs_byteswap;
target/ppc: move FP and VMX registers into aligned vsr register array The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vector operations, recreate the same layout using an aligned version of the existing vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. This also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-02 10:14:22 +01:00
ppc_avr_t *avr = cpu_avr_ptr(&cpu->env, i);
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
#if HOST_BIG_ENDIAN
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
needs_byteswap = s->dump_info.d_endian == ELFDATA2LSB;
#else
needs_byteswap = s->dump_info.d_endian == ELFDATA2MSB;
#endif
if (needs_byteswap) {
target/ppc: move FP and VMX registers into aligned vsr register array The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vector operations, recreate the same layout using an aligned version of the existing vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. This also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-02 10:14:22 +01:00
vmxregset->avr[i].u64[0] = bswap64(avr->u64[1]);
vmxregset->avr[i].u64[1] = bswap64(avr->u64[0]);
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
} else {
target/ppc: move FP and VMX registers into aligned vsr register array The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vector operations, recreate the same layout using an aligned version of the existing vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. This also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-02 10:14:22 +01:00
vmxregset->avr[i].u64[0] = avr->u64[0];
vmxregset->avr[i].u64[1] = avr->u64[1];
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
}
}
vmxregset->vscr.u32[3] = cpu_to_dump32(s, ppc_get_vscr(&cpu->env));
}
static void ppc_write_elf_vsxregset(NoteFuncArg *arg, PowerPCCPU *cpu)
{
int i;
struct PPCElfVsxregset *vsxregset;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
Note *note = &arg->note;
DumpState *s = arg->state;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
note->hdr.n_type = cpu_to_dump32(s, NT_PPC_VSX);
vsxregset = &note->contents.vsxregset;
memset(vsxregset, 0, sizeof(*vsxregset));
for (i = 0; i < 32; i++) {
target/ppc: move FP and VMX registers into aligned vsr register array The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vector operations, recreate the same layout using an aligned version of the existing vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. This also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-02 10:14:22 +01:00
uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
vsxregset->vsr[i] = cpu_to_dump64(s, *vsrl);
}
}
static void ppc_write_elf_speregset(NoteFuncArg *arg, PowerPCCPU *cpu)
{
struct PPCElfSperegset *speregset;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
Note *note = &arg->note;
DumpState *s = arg->state;
note->hdr.n_type = cpu_to_dump32(s, NT_PPC_SPE);
speregset = &note->contents.speregset;
memset(speregset, 0, sizeof(*speregset));
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
speregset->spe_acc = cpu_to_dump64(s, cpu->env.spe_acc);
speregset->spe_fscr = cpu_to_dump32(s, cpu->env.spe_fscr);
}
static const struct NoteFuncDescStruct {
int contents_size;
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
void (*note_contents_func)(NoteFuncArg *arg, PowerPCCPU *cpu);
} note_func[] = {
{sizeof_field(Note, contents.prstatus), ppc_write_elf_prstatus},
{sizeof_field(Note, contents.fpregset), ppc_write_elf_fpregset},
{sizeof_field(Note, contents.vmxregset), ppc_write_elf_vmxregset},
{sizeof_field(Note, contents.vsxregset), ppc_write_elf_vsxregset},
{sizeof_field(Note, contents.speregset), ppc_write_elf_speregset},
{ 0, NULL}
};
typedef struct NoteFuncDescStruct NoteFuncDesc;
int cpu_get_dump_info(ArchDumpInfo *info,
const struct GuestPhysBlockList *guest_phys_blocks)
{
PowerPCCPU *cpu;
if (first_cpu == NULL) {
return -1;
}
cpu = POWERPC_CPU(first_cpu);
info->d_machine = PPC_ELF_MACHINE;
info->d_class = ELFCLASS;
if (ppc_interrupts_little_endian(cpu, cpu->env.has_hv_mode)) {
info->d_endian = ELFDATA2LSB;
target/ppc: Introduce ppc_interrupts_little_endian() PowerPC CPUs use big endian by default but starting with POWER7, server grade CPUs use the ILE bit of the LPCR special purpose register to decide on the endianness to use when handling interrupts. This gives a clue to QEMU on the endianness the guest kernel is running, which is needed when generating an ELF dump of the guest or when delivering an FWNMI machine check interrupt. Commit 382d2db62bcb ("target-ppc: Introduce callback for interrupt endianness") added a class method to PowerPCCPUClass to modelize this : default implementation returns a fixed "big endian" value, while POWER7 and newer do the LPCR_ILE check. This is suboptimal as it forces to implement the method for every new CPU family, and it is very unlikely that this will ever be different than what we have today. We basically only have three cases to consider: a) CPU doesn't have an LPCR => big endian b) CPU has an LPCR but doesn't support the ILE bit => big endian c) CPU has an LPCR and supports the ILE bit => little or big endian Instead of class methods, introduce an inline helper that checks the ILE bit in the LPCR_MASK to decide on the outcome. The new helper words little endian instead of big endian. This allows to drop a ! operator in ppc_cpu_do_fwnmi_machine_check(). Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20210622140926.677618-2-groug@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-22 16:09:25 +02:00
} else {
info->d_endian = ELFDATA2MSB;
}
/* 64KB is the max page size for pseries kernel */
if (strncmp(object_get_typename(qdev_get_machine()),
"pseries-", 8) == 0) {
info->page_size = (1U << 16);
}
return 0;
}
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
int name_size = 8; /* "CORE" or "QEMU" rounded */
size_t elf_note_size = 0;
int note_head_size;
const NoteFuncDesc *nf;
note_head_size = sizeof(Elf_Nhdr);
for (nf = note_func; nf->note_contents_func; nf++) {
elf_note_size = elf_note_size + note_head_size + name_size +
nf->contents_size;
}
return (elf_note_size) * nr_cpus;
}
static int ppc_write_all_elf_notes(const char *note_name,
WriteCoreDumpFunction f,
PowerPCCPU *cpu, int id,
void *opaque)
{
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
NoteFuncArg arg = { .state = opaque };
int ret = -1;
int note_size;
const NoteFuncDesc *nf;
for (nf = note_func; nf->note_contents_func; nf++) {
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
arg.note.hdr.n_namesz = cpu_to_dump32(opaque, sizeof(arg.note.name));
arg.note.hdr.n_descsz = cpu_to_dump32(opaque, nf->contents_size);
strncpy(arg.note.name, note_name, sizeof(arg.note.name));
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
(*nf->note_contents_func)(&arg, cpu);
target-ppc: Support dump for little endian ppc64 Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-19 19:58:35 +02:00
note_size =
sizeof(arg.note) - sizeof(arg.note.contents) + nf->contents_size;
ret = f(&arg.note, note_size, opaque);
if (ret < 0) {
return -1;
}
}
return 0;
}
int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
return ppc_write_all_elf_notes("CORE", f, cpu, cpuid, opaque);
}
int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
return ppc_write_all_elf_notes("CORE", f, cpu, cpuid, opaque);
}