2017-08-20 19:23:05 +02:00
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/*
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* PPC4xx I2C controller emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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2017-12-16 23:42:14 +01:00
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016 BALATON Zoltan
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2017-08-20 19:23:05 +02:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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2017-12-16 23:42:14 +01:00
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#include "qemu/log.h"
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2017-08-20 19:23:05 +02:00
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#include "cpu.h"
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#include "hw/hw.h"
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2017-08-20 19:23:05 +02:00
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#include "hw/i2c/ppc4xx_i2c.h"
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2017-08-20 19:23:05 +02:00
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2017-12-16 23:42:14 +01:00
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#define PPC4xx_I2C_MEM_SIZE 0x12
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2017-08-20 19:23:05 +02:00
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2017-12-16 23:42:14 +01:00
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#define IIC_CNTL_PT (1 << 0)
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#define IIC_CNTL_READ (1 << 1)
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#define IIC_CNTL_CHT (1 << 2)
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#define IIC_CNTL_RPST (1 << 3)
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#define IIC_STS_PT (1 << 0)
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#define IIC_STS_ERR (1 << 2)
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#define IIC_STS_MDBS (1 << 5)
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#define IIC_EXTSTS_XFRA (1 << 0)
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#define IIC_XTCNTLSS_SRST (1 << 0)
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static void ppc4xx_i2c_reset(DeviceState *s)
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{
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PPC4xxI2CState *i2c = PPC4xx_I2C(s);
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/* FIXME: Should also reset bus?
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*if (s->address != ADDR_RESET) {
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* i2c_end_transfer(s->bus);
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*}
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*/
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i2c->mdata = 0;
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i2c->lmadr = 0;
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i2c->hmadr = 0;
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i2c->cntl = 0;
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i2c->mdcntl = 0;
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i2c->sts = 0;
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i2c->extsts = 0x8f;
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i2c->sdata = 0;
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i2c->lsadr = 0;
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i2c->hsadr = 0;
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i2c->clkdiv = 0;
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i2c->intrmsk = 0;
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i2c->xfrcnt = 0;
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i2c->xtcntlss = 0;
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i2c->directcntl = 0x0f;
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i2c->intr = 0;
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}
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static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c)
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{
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return true;
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}
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2017-08-20 19:23:05 +02:00
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2017-08-20 19:23:05 +02:00
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static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
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2017-08-20 19:23:05 +02:00
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{
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2017-08-20 19:23:05 +02:00
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PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
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uint64_t ret;
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2017-08-20 19:23:05 +02:00
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switch (addr) {
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case 0x00:
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ret = i2c->mdata;
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2017-12-16 23:42:14 +01:00
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if (ppc4xx_i2c_is_master(i2c)) {
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ret = 0xff;
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if (!(i2c->sts & IIC_STS_MDBS)) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
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"without starting transfer\n",
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TYPE_PPC4xx_I2C, __func__);
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} else {
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int pending = (i2c->cntl >> 4) & 3;
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/* get the next byte */
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int byte = i2c_recv(i2c->bus);
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if (byte < 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
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"for device 0x%02x\n", TYPE_PPC4xx_I2C,
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__func__, i2c->lmadr);
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ret = 0xff;
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} else {
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ret = byte;
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/* Raise interrupt if enabled */
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/*ppc4xx_i2c_raise_interrupt(i2c)*/;
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}
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if (!pending) {
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i2c->sts &= ~IIC_STS_MDBS;
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/*i2c_end_transfer(i2c->bus);*/
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/*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/
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} else if (pending) {
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/* current smbus implementation doesn't like
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multibyte xfer repeated start */
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i2c_end_transfer(i2c->bus);
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if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
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/* if non zero is returned, the adress is not valid */
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i2c->sts &= ~IIC_STS_PT;
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i2c->sts |= IIC_STS_ERR;
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i2c->extsts |= IIC_EXTSTS_XFRA;
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} else {
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/*i2c->sts |= IIC_STS_PT;*/
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i2c->sts |= IIC_STS_MDBS;
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i2c->sts &= ~IIC_STS_ERR;
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i2c->extsts = 0;
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}
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}
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pending--;
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i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4);
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}
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} else {
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qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
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TYPE_PPC4xx_I2C, __func__);
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}
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2017-08-20 19:23:05 +02:00
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break;
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case 0x02:
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ret = i2c->sdata;
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break;
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case 0x04:
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ret = i2c->lmadr;
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break;
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case 0x05:
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ret = i2c->hmadr;
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break;
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case 0x06:
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ret = i2c->cntl;
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break;
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case 0x07:
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ret = i2c->mdcntl;
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break;
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case 0x08:
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ret = i2c->sts;
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break;
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case 0x09:
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ret = i2c->extsts;
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break;
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case 0x0A:
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ret = i2c->lsadr;
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break;
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case 0x0B:
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ret = i2c->hsadr;
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break;
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case 0x0C:
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ret = i2c->clkdiv;
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break;
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case 0x0D:
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ret = i2c->intrmsk;
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break;
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case 0x0E:
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ret = i2c->xfrcnt;
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break;
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case 0x0F:
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ret = i2c->xtcntlss;
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break;
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case 0x10:
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ret = i2c->directcntl;
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break;
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2017-12-16 23:42:14 +01:00
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case 0x11:
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ret = i2c->intr;
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break;
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2017-08-20 19:23:05 +02:00
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default:
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2017-12-16 23:42:14 +01:00
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
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HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr);
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ret = 0;
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2017-08-20 19:23:05 +02:00
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break;
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}
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return ret;
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}
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2017-08-20 19:23:05 +02:00
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static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
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unsigned int size)
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2017-08-20 19:23:05 +02:00
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{
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2017-08-20 19:23:05 +02:00
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PPC4xxI2CState *i2c = opaque;
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2017-12-16 23:42:14 +01:00
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2017-08-20 19:23:05 +02:00
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switch (addr) {
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case 0x00:
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i2c->mdata = value;
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2017-12-16 23:42:14 +01:00
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if (!i2c_bus_busy(i2c->bus)) {
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/* assume we start a write transfer */
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if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) {
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/* if non zero is returned, the adress is not valid */
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i2c->sts &= ~IIC_STS_PT;
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i2c->sts |= IIC_STS_ERR;
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i2c->extsts |= IIC_EXTSTS_XFRA;
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} else {
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i2c->sts |= IIC_STS_PT;
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i2c->sts &= ~IIC_STS_ERR;
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i2c->extsts = 0;
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}
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}
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if (i2c_bus_busy(i2c->bus)) {
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if (i2c_send(i2c->bus, i2c->mdata)) {
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/* if the target return non zero then end the transfer */
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i2c->sts &= ~IIC_STS_PT;
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i2c->sts |= IIC_STS_ERR;
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i2c->extsts |= IIC_EXTSTS_XFRA;
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i2c_end_transfer(i2c->bus);
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}
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}
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2017-08-20 19:23:05 +02:00
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break;
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case 0x02:
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i2c->sdata = value;
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break;
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case 0x04:
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i2c->lmadr = value;
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2017-12-16 23:42:14 +01:00
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if (i2c_bus_busy(i2c->bus)) {
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i2c_end_transfer(i2c->bus);
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}
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2017-08-20 19:23:05 +02:00
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break;
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case 0x05:
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i2c->hmadr = value;
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break;
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case 0x06:
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i2c->cntl = value;
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2017-12-16 23:42:14 +01:00
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if (i2c->cntl & IIC_CNTL_PT) {
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if (i2c->cntl & IIC_CNTL_READ) {
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if (i2c_bus_busy(i2c->bus)) {
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/* end previous transfer */
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i2c->sts &= ~IIC_STS_PT;
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i2c_end_transfer(i2c->bus);
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}
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if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
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/* if non zero is returned, the adress is not valid */
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i2c->sts &= ~IIC_STS_PT;
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i2c->sts |= IIC_STS_ERR;
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i2c->extsts |= IIC_EXTSTS_XFRA;
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} else {
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/*i2c->sts |= IIC_STS_PT;*/
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i2c->sts |= IIC_STS_MDBS;
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i2c->sts &= ~IIC_STS_ERR;
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i2c->extsts = 0;
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}
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} else {
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/* we actually already did the write transfer... */
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i2c->sts &= ~IIC_STS_PT;
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}
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}
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2017-08-20 19:23:05 +02:00
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break;
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case 0x07:
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i2c->mdcntl = value & 0xDF;
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break;
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case 0x08:
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i2c->sts &= ~(value & 0x0A);
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break;
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case 0x09:
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i2c->extsts &= ~(value & 0x8F);
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break;
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case 0x0A:
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i2c->lsadr = value;
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2017-12-16 23:42:14 +01:00
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/*i2c_set_slave_address(i2c->bus, i2c->lsadr);*/
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2017-08-20 19:23:05 +02:00
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break;
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case 0x0B:
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i2c->hsadr = value;
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break;
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case 0x0C:
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i2c->clkdiv = value;
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break;
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case 0x0D:
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i2c->intrmsk = value;
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break;
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case 0x0E:
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i2c->xfrcnt = value & 0x77;
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break;
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case 0x0F:
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2017-12-16 23:42:14 +01:00
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if (value & IIC_XTCNTLSS_SRST) {
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/* Is it actually a full reset? U-Boot sets some regs before */
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ppc4xx_i2c_reset(DEVICE(i2c));
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break;
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}
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2017-08-20 19:23:05 +02:00
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i2c->xtcntlss = value;
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break;
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case 0x10:
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i2c->directcntl = value & 0x7;
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break;
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2017-12-16 23:42:14 +01:00
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case 0x11:
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i2c->intr = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
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HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr);
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break;
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2017-08-20 19:23:05 +02:00
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}
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}
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2017-08-20 19:23:05 +02:00
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static const MemoryRegionOps ppc4xx_i2c_ops = {
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.read = ppc4xx_i2c_readb,
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.write = ppc4xx_i2c_writeb,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 1,
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2017-08-20 19:23:05 +02:00
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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2017-08-20 19:23:05 +02:00
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static void ppc4xx_i2c_init(Object *o)
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2017-08-20 19:23:05 +02:00
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{
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2017-08-20 19:23:05 +02:00
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PPC4xxI2CState *s = PPC4xx_I2C(o);
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2017-08-20 19:23:05 +02:00
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2017-08-20 19:23:05 +02:00
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memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
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TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
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s->bus = i2c_init_bus(DEVICE(s), "i2c");
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2017-08-20 19:23:05 +02:00
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}
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2017-08-20 19:23:05 +02:00
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static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = ppc4xx_i2c_reset;
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}
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static const TypeInfo ppc4xx_i2c_type_info = {
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.name = TYPE_PPC4xx_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PPC4xxI2CState),
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.instance_init = ppc4xx_i2c_init,
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.class_init = ppc4xx_i2c_class_init,
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};
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static void ppc4xx_i2c_register_types(void)
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{
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type_register_static(&ppc4xx_i2c_type_info);
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}
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type_init(ppc4xx_i2c_register_types)
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