2021-02-08 06:45:54 +01:00
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/exec-all.h"
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#include "qapi/error.h"
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#include "hw/qdev-properties.h"
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2021-04-09 03:07:38 +02:00
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#include "fpu/softfloat-helpers.h"
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2021-02-08 06:45:54 +01:00
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static void hexagon_v67_cpu_init(Object *obj)
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{
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}
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static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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char **cpuname;
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cpuname = g_strsplit(cpu_model, ",", 1);
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typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]);
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oc = object_class_by_name(typename);
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g_strfreev(cpuname);
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g_free(typename);
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if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL;
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}
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return oc;
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}
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static Property hexagon_lldb_compat_property =
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DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false);
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static Property hexagon_lldb_stack_adjust_property =
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DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,
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0, qdev_prop_uint32, target_ulong);
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const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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"sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1",
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"usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15",
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"c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "c22", "c23",
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"c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31",
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};
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/*
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* One of the main debugging techniques is to use "-d cpu" and compare against
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* LLDB output when single stepping. However, the target and qemu put the
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* stacks at different locations. This is used to compensate so the diff is
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* cleaner.
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*/
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2021-04-09 03:07:31 +02:00
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static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
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2021-02-08 06:45:54 +01:00
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{
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2021-04-09 03:07:32 +02:00
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HexagonCPU *cpu = env_archcpu(env);
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2021-02-08 06:45:54 +01:00
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target_ulong stack_adjust = cpu->lldb_stack_adjust;
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target_ulong stack_start = env->stack_start;
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target_ulong stack_size = 0x10000;
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if (stack_adjust == 0) {
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return addr;
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}
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if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) {
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return addr - stack_adjust;
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}
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return addr;
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}
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/* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */
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2021-04-09 03:07:31 +02:00
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static target_ulong read_p3_0(CPUHexagonState *env)
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2021-02-08 06:45:54 +01:00
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{
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int32_t control_reg = 0;
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int i;
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for (i = NUM_PREGS - 1; i >= 0; i--) {
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control_reg <<= 8;
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control_reg |= env->pred[i] & 0xff;
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}
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return control_reg;
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}
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static void print_reg(FILE *f, CPUHexagonState *env, int regnum)
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{
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target_ulong value;
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if (regnum == HEX_REG_P3_0) {
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value = read_p3_0(env);
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} else {
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value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum])
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: env->gpr[regnum];
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}
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qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n",
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hexagon_regnames[regnum], value);
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}
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static void hexagon_dump(CPUHexagonState *env, FILE *f)
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{
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2021-04-09 03:07:32 +02:00
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HexagonCPU *cpu = env_archcpu(env);
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2021-02-08 06:45:54 +01:00
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if (cpu->lldb_compat) {
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/*
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* When comparing with LLDB, it doesn't step through single-cycle
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* hardware loops the same way. So, we just skip them here
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*/
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if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) {
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return;
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}
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env->last_pc_dumped = env->gpr[HEX_REG_PC];
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}
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qemu_fprintf(f, "General Purpose Registers = {\n");
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for (int i = 0; i < 32; i++) {
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print_reg(f, env, i);
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}
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print_reg(f, env, HEX_REG_SA0);
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print_reg(f, env, HEX_REG_LC0);
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print_reg(f, env, HEX_REG_SA1);
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print_reg(f, env, HEX_REG_LC1);
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print_reg(f, env, HEX_REG_M0);
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print_reg(f, env, HEX_REG_M1);
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print_reg(f, env, HEX_REG_USR);
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print_reg(f, env, HEX_REG_P3_0);
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print_reg(f, env, HEX_REG_GP);
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print_reg(f, env, HEX_REG_UGP);
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print_reg(f, env, HEX_REG_PC);
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#ifdef CONFIG_USER_ONLY
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/*
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* Not modelled in user mode, print junk to minimize the diff's
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* with LLDB output
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*/
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qemu_fprintf(f, " cause = 0x000000db\n");
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qemu_fprintf(f, " badva = 0x00000000\n");
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qemu_fprintf(f, " cs0 = 0x00000000\n");
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qemu_fprintf(f, " cs1 = 0x00000000\n");
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#else
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print_reg(f, env, HEX_REG_CAUSE);
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print_reg(f, env, HEX_REG_BADVA);
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print_reg(f, env, HEX_REG_CS0);
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print_reg(f, env, HEX_REG_CS1);
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#endif
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qemu_fprintf(f, "}\n");
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}
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static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
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{
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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CPUHexagonState *env = &cpu->env;
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hexagon_dump(env, f);
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}
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void hexagon_debug(CPUHexagonState *env)
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{
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hexagon_dump(env, stdout);
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}
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static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
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{
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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CPUHexagonState *env = &cpu->env;
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env->gpr[HEX_REG_PC] = value;
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}
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static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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CPUHexagonState *env = &cpu->env;
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env->gpr[HEX_REG_PC] = tb->pc;
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}
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static bool hexagon_cpu_has_work(CPUState *cs)
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{
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return true;
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}
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void restore_state_to_opc(CPUHexagonState *env, TranslationBlock *tb,
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target_ulong *data)
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{
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env->gpr[HEX_REG_PC] = data[0];
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}
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static void hexagon_cpu_reset(DeviceState *dev)
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{
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CPUState *cs = CPU(dev);
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu);
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2021-04-09 03:07:38 +02:00
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CPUHexagonState *env = &cpu->env;
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2021-02-08 06:45:54 +01:00
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mcc->parent_reset(dev);
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2021-04-09 03:07:38 +02:00
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set_default_nan_mode(1, &env->fp_status);
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set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
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2021-02-08 06:45:54 +01:00
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}
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static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
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{
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info->print_insn = print_insn_hexagon;
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}
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static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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mcc->parent_realize(dev, errp);
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}
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static void hexagon_cpu_init(Object *obj)
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{
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HexagonCPU *cpu = HEXAGON_CPU(obj);
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cpu_set_cpustate_pointers(cpu);
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qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
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qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
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}
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static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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#ifdef CONFIG_USER_ONLY
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switch (access_type) {
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case MMU_INST_FETCH:
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cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE;
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break;
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case MMU_DATA_LOAD:
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cs->exception_index = HEX_EXCP_PRIV_NO_UREAD;
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break;
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case MMU_DATA_STORE:
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cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE;
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break;
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}
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cpu_loop_exit_restore(cs, retaddr);
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#else
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#error System mode not implemented for Hexagon
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#endif
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}
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#include "hw/core/tcg-cpu-ops.h"
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2021-02-28 00:21:17 +01:00
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static const struct TCGCPUOps hexagon_tcg_ops = {
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2021-02-08 06:45:54 +01:00
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.initialize = hexagon_translate_init,
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.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
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.tlb_fill = hexagon_tlb_fill,
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};
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static void hexagon_cpu_class_init(ObjectClass *c, void *data)
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{
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HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
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CPUClass *cc = CPU_CLASS(c);
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DeviceClass *dc = DEVICE_CLASS(c);
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device_class_set_parent_realize(dc, hexagon_cpu_realize,
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&mcc->parent_realize);
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device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset);
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cc->class_by_name = hexagon_cpu_class_by_name;
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cc->has_work = hexagon_cpu_has_work;
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cc->dump_state = hexagon_dump_state;
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cc->set_pc = hexagon_cpu_set_pc;
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cc->gdb_read_register = hexagon_gdb_read_register;
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cc->gdb_write_register = hexagon_gdb_write_register;
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cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS;
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cc->gdb_stop_before_watchpoint = true;
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cc->disas_set_info = hexagon_cpu_disas_set_info;
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cc->tcg_ops = &hexagon_tcg_ops;
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}
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#define DEFINE_CPU(type_name, initfn) \
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{ \
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.name = type_name, \
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.parent = TYPE_HEXAGON_CPU, \
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.instance_init = initfn \
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}
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static const TypeInfo hexagon_cpu_type_infos[] = {
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{
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.name = TYPE_HEXAGON_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(HexagonCPU),
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.instance_init = hexagon_cpu_init,
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.abstract = true,
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.class_size = sizeof(HexagonCPUClass),
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.class_init = hexagon_cpu_class_init,
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},
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DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),
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};
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DEFINE_TYPES(hexagon_cpu_type_infos)
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