2016-09-29 12:32:44 +02:00
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/*
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* libqos PCI bindings for SPAPR
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/pci-spapr.h"
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#include "libqos/rtas.h"
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#include "hw/pci/pci_regs.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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/* From include/hw/pci-host/spapr.h */
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2016-10-12 04:30:07 +02:00
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typedef struct QPCIWindow {
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uint64_t pci_base; /* window address in PCI space */
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uint64_t size; /* window size */
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} QPCIWindow;
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2016-09-29 12:32:44 +02:00
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typedef struct QPCIBusSPAPR {
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QPCIBus bus;
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QGuestAllocator *alloc;
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2016-10-12 04:30:07 +02:00
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uint64_t buid;
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uint64_t pio_cpu_base;
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QPCIWindow pio;
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uint64_t mmio_cpu_base;
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QPCIWindow mmio;
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2016-09-29 12:32:44 +02:00
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uint64_t pci_hole_start;
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uint64_t pci_hole_size;
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uint64_t pci_hole_alloc;
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uint32_t pci_iohole_start;
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uint32_t pci_iohole_size;
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uint32_t pci_iohole_alloc;
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} QPCIBusSPAPR;
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/*
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* PCI devices are always little-endian
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* SPAPR by default is big-endian
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* so PCI accessors need to swap data endianness
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*/
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static uint8_t qpci_spapr_io_readb(QPCIBus *bus, void *addr)
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2016-09-29 12:32:44 +02:00
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uint64_t port = (uintptr_t)addr;
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uint8_t v;
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2016-10-12 04:30:07 +02:00
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if (port < s->pio.size) {
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v = readb(s->pio_cpu_base + port);
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2016-09-29 12:32:44 +02:00
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} else {
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2016-10-12 04:30:07 +02:00
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v = readb(s->mmio_cpu_base + port);
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2016-09-29 12:32:44 +02:00
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}
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return v;
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}
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static uint16_t qpci_spapr_io_readw(QPCIBus *bus, void *addr)
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2016-09-29 12:32:44 +02:00
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uint64_t port = (uintptr_t)addr;
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uint16_t v;
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2016-10-12 04:30:07 +02:00
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if (port < s->pio.size) {
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v = readw(s->pio_cpu_base + port);
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2016-09-29 12:32:44 +02:00
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} else {
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2016-10-12 04:30:07 +02:00
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v = readw(s->mmio_cpu_base + port);
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2016-09-29 12:32:44 +02:00
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}
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return bswap16(v);
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}
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static uint32_t qpci_spapr_io_readl(QPCIBus *bus, void *addr)
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2016-09-29 12:32:44 +02:00
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uint64_t port = (uintptr_t)addr;
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uint32_t v;
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2016-10-12 04:30:07 +02:00
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if (port < s->pio.size) {
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v = readl(s->pio_cpu_base + port);
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2016-09-29 12:32:44 +02:00
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} else {
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2016-10-12 04:30:07 +02:00
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v = readl(s->mmio_cpu_base + port);
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2016-09-29 12:32:44 +02:00
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}
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return bswap32(v);
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}
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static void qpci_spapr_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2016-09-29 12:32:44 +02:00
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uint64_t port = (uintptr_t)addr;
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2016-10-12 04:30:07 +02:00
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if (port < s->pio.size) {
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writeb(s->pio_cpu_base + port, value);
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2016-09-29 12:32:44 +02:00
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} else {
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2016-10-12 04:30:07 +02:00
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writeb(s->mmio_cpu_base + port, value);
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2016-09-29 12:32:44 +02:00
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}
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}
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static void qpci_spapr_io_writew(QPCIBus *bus, void *addr, uint16_t value)
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2016-09-29 12:32:44 +02:00
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uint64_t port = (uintptr_t)addr;
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value = bswap16(value);
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2016-10-12 04:30:07 +02:00
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if (port < s->pio.size) {
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writew(s->pio_cpu_base + port, value);
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2016-09-29 12:32:44 +02:00
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} else {
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2016-10-12 04:30:07 +02:00
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writew(s->mmio_cpu_base + port, value);
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2016-09-29 12:32:44 +02:00
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}
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}
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static void qpci_spapr_io_writel(QPCIBus *bus, void *addr, uint32_t value)
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2016-09-29 12:32:44 +02:00
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uint64_t port = (uintptr_t)addr;
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value = bswap32(value);
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2016-10-12 04:30:07 +02:00
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if (port < s->pio.size) {
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writel(s->pio_cpu_base + port, value);
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2016-09-29 12:32:44 +02:00
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} else {
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2016-10-12 04:30:07 +02:00
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writel(s->mmio_cpu_base + port, value);
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2016-09-29 12:32:44 +02:00
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}
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}
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static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2016-10-12 04:30:07 +02:00
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return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 1);
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2016-09-29 12:32:44 +02:00
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}
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static uint16_t qpci_spapr_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2016-10-12 04:30:07 +02:00
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return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 2);
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2016-09-29 12:32:44 +02:00
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}
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static uint32_t qpci_spapr_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2016-10-12 04:30:07 +02:00
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return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 4);
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2016-09-29 12:32:44 +02:00
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}
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static void qpci_spapr_config_writeb(QPCIBus *bus, int devfn, uint8_t offset,
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uint8_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2016-10-12 04:30:07 +02:00
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qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 1, value);
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2016-09-29 12:32:44 +02:00
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}
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static void qpci_spapr_config_writew(QPCIBus *bus, int devfn, uint8_t offset,
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uint16_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2016-10-12 04:30:07 +02:00
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qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 2, value);
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2016-09-29 12:32:44 +02:00
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}
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static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset,
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uint32_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2016-10-12 04:30:07 +02:00
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qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 4, value);
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2016-09-29 12:32:44 +02:00
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}
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static void *qpci_spapr_iomap(QPCIBus *bus, QPCIDevice *dev, int barno,
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uint64_t *sizeptr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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static const int bar_reg_map[] = {
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PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
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PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
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};
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int bar_reg;
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uint32_t addr;
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uint64_t size;
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uint32_t io_type;
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g_assert(barno >= 0 && barno <= 5);
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bar_reg = bar_reg_map[barno];
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qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
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addr = qpci_config_readl(dev, bar_reg);
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io_type = addr & PCI_BASE_ADDRESS_SPACE;
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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addr &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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addr &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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size = (1ULL << ctzl(addr));
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if (size == 0) {
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return NULL;
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}
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if (sizeptr) {
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*sizeptr = size;
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}
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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uint16_t loc;
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g_assert(QEMU_ALIGN_UP(s->pci_iohole_alloc, size) + size
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<= s->pci_iohole_size);
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s->pci_iohole_alloc = QEMU_ALIGN_UP(s->pci_iohole_alloc, size);
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loc = s->pci_iohole_start + s->pci_iohole_alloc;
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s->pci_iohole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
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return (void *)(unsigned long)loc;
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} else {
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uint64_t loc;
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g_assert(QEMU_ALIGN_UP(s->pci_hole_alloc, size) + size
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<= s->pci_hole_size);
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s->pci_hole_alloc = QEMU_ALIGN_UP(s->pci_hole_alloc, size);
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loc = s->pci_hole_start + s->pci_hole_alloc;
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s->pci_hole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc);
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return (void *)(unsigned long)loc;
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}
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}
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static void qpci_spapr_iounmap(QPCIBus *bus, void *data)
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{
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/* FIXME */
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}
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2016-10-12 04:30:07 +02:00
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
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#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
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#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
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#define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \
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SPAPR_PCI_MEM_WIN_BUS_OFFSET)
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#define SPAPR_PCI_IO_WIN_OFF 0x80000000
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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2016-09-29 12:32:44 +02:00
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QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
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{
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QPCIBusSPAPR *ret;
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ret = g_malloc(sizeof(*ret));
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ret->alloc = alloc;
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ret->bus.io_readb = qpci_spapr_io_readb;
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ret->bus.io_readw = qpci_spapr_io_readw;
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ret->bus.io_readl = qpci_spapr_io_readl;
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ret->bus.io_writeb = qpci_spapr_io_writeb;
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ret->bus.io_writew = qpci_spapr_io_writew;
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ret->bus.io_writel = qpci_spapr_io_writel;
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ret->bus.config_readb = qpci_spapr_config_readb;
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ret->bus.config_readw = qpci_spapr_config_readw;
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ret->bus.config_readl = qpci_spapr_config_readl;
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ret->bus.config_writeb = qpci_spapr_config_writeb;
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ret->bus.config_writew = qpci_spapr_config_writew;
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ret->bus.config_writel = qpci_spapr_config_writel;
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ret->bus.iomap = qpci_spapr_iomap;
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ret->bus.iounmap = qpci_spapr_iounmap;
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2016-10-12 04:30:07 +02:00
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/* FIXME: We assume the default location of the PHB for now.
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* Ideally we'd parse the device tree deposited in the guest to
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* get the window locations */
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ret->buid = 0x800000020000000ULL;
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ret->pio_cpu_base = SPAPR_PCI_WINDOW_BASE + SPAPR_PCI_IO_WIN_OFF;
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ret->pio.pci_base = 0;
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ret->pio.size = SPAPR_PCI_IO_WIN_SIZE;
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ret->mmio_cpu_base = SPAPR_PCI_WINDOW_BASE + SPAPR_PCI_MMIO_WIN_OFF;
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ret->mmio.pci_base = SPAPR_PCI_MEM_WIN_BUS_OFFSET;
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ret->mmio.size = SPAPR_PCI_MMIO_WIN_SIZE;
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2016-09-29 12:32:44 +02:00
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ret->pci_hole_start = 0xC0000000;
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2016-10-12 04:38:25 +02:00
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ret->pci_hole_size =
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ret->mmio.pci_base + ret->mmio.size - ret->pci_hole_start;
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2016-09-29 12:32:44 +02:00
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ret->pci_hole_alloc = 0;
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ret->pci_iohole_start = 0xc000;
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2016-10-12 04:38:25 +02:00
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ret->pci_iohole_size =
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ret->pio.pci_base + ret->pio.size - ret->pci_iohole_start;
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2016-09-29 12:32:44 +02:00
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ret->pci_iohole_alloc = 0;
|
|
|
|
|
|
|
|
return &ret->bus;
|
|
|
|
}
|
|
|
|
|
|
|
|
void qpci_free_spapr(QPCIBus *bus)
|
|
|
|
{
|
|
|
|
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
|
|
|
|
|
|
|
|
g_free(s);
|
|
|
|
}
|