2016-06-28 21:05:13 +02:00
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/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "trace.h"
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#include "qemu/timer.h"
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#include "hw/ppc/spapr.h"
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2019-01-17 08:53:26 +01:00
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#include "hw/ppc/spapr_cpu_core.h"
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2016-06-28 21:05:13 +02:00
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#include "hw/ppc/xics.h"
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2019-01-10 09:18:47 +01:00
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#include "hw/ppc/xics_spapr.h"
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2016-10-20 07:07:56 +02:00
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#include "hw/ppc/fdt.h"
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2016-06-28 21:05:13 +02:00
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#include "qapi/visitor.h"
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/*
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* Guest interfaces
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*/
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2019-06-17 13:55:36 +02:00
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static bool check_emulated_xics(SpaprMachineState *spapr, const char *func)
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2019-06-13 18:44:54 +02:00
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{
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2019-06-17 13:55:36 +02:00
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if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ||
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kvm_irqchip_in_kernel()) {
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error_report("pseries: %s must only be called for emulated XICS",
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2019-06-13 18:44:54 +02:00
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func);
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2019-06-17 13:55:36 +02:00
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return false;
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2019-06-13 18:44:54 +02:00
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}
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2019-06-17 13:55:36 +02:00
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return true;
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2019-06-13 18:44:54 +02:00
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}
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2019-06-17 13:55:36 +02:00
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#define CHECK_EMULATED_XICS_HCALL(spapr) \
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do { \
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if (!check_emulated_xics((spapr), __func__)) { \
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return H_HARDWARE; \
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} \
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2019-06-13 18:44:54 +02:00
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} while (0)
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr,
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2016-06-28 21:05:13 +02:00
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target_ulong opcode, target_ulong *args)
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{
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target_ulong cppr = args[0];
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2019-06-17 13:55:36 +02:00
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CHECK_EMULATED_XICS_HCALL(spapr);
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2019-06-13 18:44:54 +02:00
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2019-01-17 08:53:26 +01:00
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icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
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2016-06-28 21:05:13 +02:00
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return H_SUCCESS;
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}
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr,
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2016-06-28 21:05:13 +02:00
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target_ulong opcode, target_ulong *args)
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{
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target_ulong mfrr = args[1];
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2017-04-03 09:45:57 +02:00
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ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
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2016-06-28 21:05:13 +02:00
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2019-06-17 13:55:36 +02:00
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CHECK_EMULATED_XICS_HCALL(spapr);
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2019-06-13 18:44:54 +02:00
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2017-02-27 15:29:25 +01:00
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if (!icp) {
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2016-06-28 21:05:13 +02:00
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return H_PARAMETER;
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}
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2017-02-27 15:29:25 +01:00
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icp_set_mfrr(icp, mfrr);
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2016-06-28 21:05:13 +02:00
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return H_SUCCESS;
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}
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr,
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2016-06-28 21:05:13 +02:00
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target_ulong opcode, target_ulong *args)
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{
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2019-01-17 08:53:26 +01:00
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uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
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2016-06-28 21:05:13 +02:00
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2019-06-17 13:55:36 +02:00
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CHECK_EMULATED_XICS_HCALL(spapr);
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2019-06-13 18:44:54 +02:00
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2016-06-28 21:05:13 +02:00
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args[0] = xirr;
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return H_SUCCESS;
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}
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr,
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2016-06-28 21:05:13 +02:00
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target_ulong opcode, target_ulong *args)
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{
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2019-01-17 08:53:26 +01:00
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uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
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2016-06-28 21:05:13 +02:00
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2019-06-17 13:55:36 +02:00
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CHECK_EMULATED_XICS_HCALL(spapr);
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2019-06-13 18:44:54 +02:00
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2016-06-28 21:05:13 +02:00
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args[0] = xirr;
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args[1] = cpu_get_host_ticks();
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return H_SUCCESS;
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}
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr,
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2016-06-28 21:05:13 +02:00
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target_ulong opcode, target_ulong *args)
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{
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target_ulong xirr = args[0];
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2019-06-17 13:55:36 +02:00
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CHECK_EMULATED_XICS_HCALL(spapr);
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2019-06-13 18:44:54 +02:00
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2019-01-17 08:53:26 +01:00
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icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
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2016-06-28 21:05:13 +02:00
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return H_SUCCESS;
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}
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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static target_ulong h_ipoll(PowerPCCPU *cpu, SpaprMachineState *spapr,
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2016-06-28 21:05:13 +02:00
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target_ulong opcode, target_ulong *args)
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{
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2019-03-14 07:38:55 +01:00
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ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
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2016-06-28 21:05:14 +02:00
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uint32_t mfrr;
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2019-03-14 07:38:55 +01:00
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uint32_t xirr;
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2019-06-17 13:55:36 +02:00
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CHECK_EMULATED_XICS_HCALL(spapr);
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2019-06-13 18:44:54 +02:00
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2019-03-14 07:38:55 +01:00
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if (!icp) {
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return H_PARAMETER;
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}
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xirr = icp_ipoll(icp, &mfrr);
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2016-06-28 21:05:13 +02:00
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2016-06-28 21:05:14 +02:00
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args[0] = xirr;
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args[1] = mfrr;
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2016-06-28 21:05:13 +02:00
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return H_SUCCESS;
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}
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2019-06-17 13:55:36 +02:00
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#define CHECK_EMULATED_XICS_RTAS(spapr, rets) \
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do { \
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if (!check_emulated_xics((spapr), __func__)) { \
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rtas_st((rets), 0, RTAS_OUT_HW_ERROR); \
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return; \
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} \
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2019-06-13 18:44:54 +02:00
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} while (0)
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|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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|
static void rtas_set_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
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2016-06-28 21:05:13 +02:00
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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2017-02-27 15:29:12 +01:00
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ICSState *ics = spapr->ics;
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2016-10-03 09:24:47 +02:00
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uint32_t nr, srcno, server, priority;
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2016-06-28 21:05:13 +02:00
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2019-06-17 13:55:36 +02:00
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CHECK_EMULATED_XICS_RTAS(spapr, rets);
|
2019-06-13 18:44:54 +02:00
|
|
|
|
2016-06-28 21:05:13 +02:00
|
|
|
if ((nargs != 3) || (nret != 1)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-10-03 09:24:46 +02:00
|
|
|
if (!ics) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-06-28 21:05:13 +02:00
|
|
|
|
|
|
|
|
nr = rtas_ld(args, 0);
|
2017-04-03 09:45:57 +02:00
|
|
|
server = rtas_ld(args, 1);
|
2016-06-28 21:05:13 +02:00
|
|
|
priority = rtas_ld(args, 2);
|
|
|
|
|
|
2017-02-27 15:29:25 +01:00
|
|
|
if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
|
2016-06-28 21:05:13 +02:00
|
|
|
|| (priority > 0xff)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-03 09:24:47 +02:00
|
|
|
srcno = nr - ics->offset;
|
2019-09-24 06:13:39 +02:00
|
|
|
ics_write_xive(ics, srcno, server, priority, priority);
|
2016-06-28 21:05:13 +02:00
|
|
|
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
static void rtas_get_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
2016-06-28 21:05:13 +02:00
|
|
|
uint32_t token,
|
|
|
|
|
uint32_t nargs, target_ulong args,
|
|
|
|
|
uint32_t nret, target_ulong rets)
|
|
|
|
|
{
|
2017-02-27 15:29:12 +01:00
|
|
|
ICSState *ics = spapr->ics;
|
2016-10-03 09:24:47 +02:00
|
|
|
uint32_t nr, srcno;
|
2016-06-28 21:05:13 +02:00
|
|
|
|
2019-06-17 13:55:36 +02:00
|
|
|
CHECK_EMULATED_XICS_RTAS(spapr, rets);
|
2019-06-13 18:44:54 +02:00
|
|
|
|
2016-06-28 21:05:13 +02:00
|
|
|
if ((nargs != 1) || (nret != 3)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-10-03 09:24:46 +02:00
|
|
|
if (!ics) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-06-28 21:05:13 +02:00
|
|
|
|
|
|
|
|
nr = rtas_ld(args, 0);
|
|
|
|
|
|
|
|
|
|
if (!ics_valid_irq(ics, nr)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
2016-10-03 09:24:47 +02:00
|
|
|
srcno = nr - ics->offset;
|
|
|
|
|
rtas_st(rets, 1, ics->irqs[srcno].server);
|
|
|
|
|
rtas_st(rets, 2, ics->irqs[srcno].priority);
|
2016-06-28 21:05:13 +02:00
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
static void rtas_int_off(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
2016-06-28 21:05:13 +02:00
|
|
|
uint32_t token,
|
|
|
|
|
uint32_t nargs, target_ulong args,
|
|
|
|
|
uint32_t nret, target_ulong rets)
|
|
|
|
|
{
|
2017-02-27 15:29:12 +01:00
|
|
|
ICSState *ics = spapr->ics;
|
2016-10-03 09:24:47 +02:00
|
|
|
uint32_t nr, srcno;
|
2016-06-28 21:05:13 +02:00
|
|
|
|
2019-06-17 13:55:36 +02:00
|
|
|
CHECK_EMULATED_XICS_RTAS(spapr, rets);
|
2019-06-13 18:44:54 +02:00
|
|
|
|
2016-06-28 21:05:13 +02:00
|
|
|
if ((nargs != 1) || (nret != 1)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-10-03 09:24:46 +02:00
|
|
|
if (!ics) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-06-28 21:05:13 +02:00
|
|
|
|
|
|
|
|
nr = rtas_ld(args, 0);
|
|
|
|
|
|
|
|
|
|
if (!ics_valid_irq(ics, nr)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-03 09:24:47 +02:00
|
|
|
srcno = nr - ics->offset;
|
2019-09-24 06:13:39 +02:00
|
|
|
ics_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
|
|
|
|
|
ics->irqs[srcno].priority);
|
2016-06-28 21:05:13 +02:00
|
|
|
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
static void rtas_int_on(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
2016-06-28 21:05:13 +02:00
|
|
|
uint32_t token,
|
|
|
|
|
uint32_t nargs, target_ulong args,
|
|
|
|
|
uint32_t nret, target_ulong rets)
|
|
|
|
|
{
|
2017-02-27 15:29:12 +01:00
|
|
|
ICSState *ics = spapr->ics;
|
2016-10-03 09:24:47 +02:00
|
|
|
uint32_t nr, srcno;
|
2016-06-28 21:05:13 +02:00
|
|
|
|
2019-06-17 13:55:36 +02:00
|
|
|
CHECK_EMULATED_XICS_RTAS(spapr, rets);
|
2019-06-13 18:44:54 +02:00
|
|
|
|
2016-06-28 21:05:13 +02:00
|
|
|
if ((nargs != 1) || (nret != 1)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-10-03 09:24:46 +02:00
|
|
|
if (!ics) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-06-28 21:05:13 +02:00
|
|
|
|
|
|
|
|
nr = rtas_ld(args, 0);
|
|
|
|
|
|
|
|
|
|
if (!ics_valid_irq(ics, nr)) {
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-03 09:24:47 +02:00
|
|
|
srcno = nr - ics->offset;
|
2019-09-24 06:13:39 +02:00
|
|
|
ics_write_xive(ics, srcno, ics->irqs[srcno].server,
|
|
|
|
|
ics->irqs[srcno].saved_priority,
|
|
|
|
|
ics->irqs[srcno].saved_priority);
|
2016-06-28 21:05:13 +02:00
|
|
|
|
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-24 07:51:55 +02:00
|
|
|
static void ics_spapr_realize(DeviceState *dev, Error **errp)
|
2016-06-28 21:05:13 +02:00
|
|
|
{
|
2019-09-24 07:51:55 +02:00
|
|
|
ICSState *ics = ICS_SPAPR(dev);
|
|
|
|
|
ICSStateClass *icsc = ICS_GET_CLASS(ics);
|
|
|
|
|
Error *local_err = NULL;
|
|
|
|
|
|
|
|
|
|
icsc->parent_realize(dev, &local_err);
|
|
|
|
|
if (local_err) {
|
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-28 21:05:13 +02:00
|
|
|
spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
|
|
|
|
|
spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
|
|
|
|
|
spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
|
|
|
|
|
spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
|
|
|
|
|
|
|
|
|
|
spapr_register_hypercall(H_CPPR, h_cppr);
|
|
|
|
|
spapr_register_hypercall(H_IPI, h_ipi);
|
|
|
|
|
spapr_register_hypercall(H_XIRR, h_xirr);
|
|
|
|
|
spapr_register_hypercall(H_XIRR_X, h_xirr_x);
|
|
|
|
|
spapr_register_hypercall(H_EOI, h_eoi);
|
|
|
|
|
spapr_register_hypercall(H_IPOLL, h_ipoll);
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-30 04:35:06 +02:00
|
|
|
static void xics_spapr_dt(SpaprInterruptController *intc, uint32_t nr_servers,
|
|
|
|
|
void *fdt, uint32_t phandle)
|
2016-10-20 07:07:56 +02:00
|
|
|
{
|
|
|
|
|
uint32_t interrupt_server_ranges_prop[] = {
|
2017-02-27 15:29:26 +01:00
|
|
|
0, cpu_to_be32(nr_servers),
|
2016-10-20 07:07:56 +02:00
|
|
|
};
|
|
|
|
|
int node;
|
|
|
|
|
|
2019-09-23 07:19:28 +02:00
|
|
|
_FDT(node = fdt_add_subnode(fdt, 0, "interrupt-controller"));
|
2016-10-20 07:07:56 +02:00
|
|
|
|
|
|
|
|
_FDT(fdt_setprop_string(fdt, node, "device_type",
|
|
|
|
|
"PowerPC-External-Interrupt-Presentation"));
|
|
|
|
|
_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
|
|
|
|
|
_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
|
|
|
|
|
_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
|
|
|
|
|
interrupt_server_ranges_prop,
|
|
|
|
|
sizeof(interrupt_server_ranges_prop)));
|
|
|
|
|
_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
|
|
|
|
|
_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
|
|
|
|
|
_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
|
|
|
|
|
}
|
2019-09-24 07:51:55 +02:00
|
|
|
|
2019-09-26 06:11:23 +02:00
|
|
|
static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc,
|
|
|
|
|
PowerPCCPU *cpu, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
ICSState *ics = ICS_SPAPR(intc);
|
|
|
|
|
Object *obj;
|
|
|
|
|
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
|
|
|
|
|
|
|
|
|
|
obj = icp_create(OBJECT(cpu), TYPE_ICP, ics->xics, errp);
|
|
|
|
|
if (!obj) {
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spapr_cpu->icp = ICP(obj);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-22 18:38:10 +02:00
|
|
|
static void xics_spapr_cpu_intc_reset(SpaprInterruptController *intc,
|
|
|
|
|
PowerPCCPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
icp_reset(spapr_cpu_state(cpu)->icp);
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-24 16:27:22 +02:00
|
|
|
static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc,
|
|
|
|
|
PowerPCCPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
|
|
|
|
|
|
|
|
|
|
icp_destroy(spapr_cpu->icp);
|
|
|
|
|
spapr_cpu->icp = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-26 06:31:13 +02:00
|
|
|
static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq,
|
|
|
|
|
bool lsi, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
ICSState *ics = ICS_SPAPR(intc);
|
|
|
|
|
|
|
|
|
|
assert(ics);
|
|
|
|
|
assert(ics_valid_irq(ics, irq));
|
|
|
|
|
|
|
|
|
|
if (!ics_irq_free(ics, irq - ics->offset)) {
|
|
|
|
|
error_setg(errp, "IRQ %d is not free", irq);
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ics_set_irq_type(ics, irq - ics->offset, lsi);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void xics_spapr_free_irq(SpaprInterruptController *intc, int irq)
|
|
|
|
|
{
|
|
|
|
|
ICSState *ics = ICS_SPAPR(intc);
|
|
|
|
|
uint32_t srcno = irq - ics->offset;
|
|
|
|
|
|
|
|
|
|
assert(ics_valid_irq(ics, irq));
|
|
|
|
|
|
|
|
|
|
memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState));
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}
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2019-09-26 08:09:46 +02:00
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static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val)
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{
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ICSState *ics = ICS_SPAPR(intc);
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uint32_t srcno = irq - ics->offset;
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ics_set_irq(ics, srcno, val);
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}
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2019-09-26 08:12:05 +02:00
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static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon)
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{
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ICSState *ics = ICS_SPAPR(intc);
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
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}
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ics_pic_print_info(ics, mon);
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}
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2019-09-27 02:53:53 +02:00
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static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
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{
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if (!kvm_irqchip_in_kernel()) {
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_resend(spapr_cpu_state(cpu)->icp);
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}
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}
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return 0;
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}
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2019-11-26 17:46:23 +01:00
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static int xics_spapr_activate(SpaprInterruptController *intc,
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uint32_t nr_servers, Error **errp)
|
2019-09-26 15:58:36 +02:00
|
|
|
{
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|
|
|
|
if (kvm_enabled()) {
|
2019-11-26 17:46:23 +01:00
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return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp);
|
2019-09-26 15:58:36 +02:00
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}
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return 0;
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}
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static void xics_spapr_deactivate(SpaprInterruptController *intc)
|
|
|
|
|
{
|
|
|
|
|
if (kvm_irqchip_in_kernel()) {
|
|
|
|
|
xics_kvm_disconnect(intc);
|
|
|
|
|
}
|
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|
|
|
}
|
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|
|
|
2019-09-24 07:51:55 +02:00
|
|
|
static void ics_spapr_class_init(ObjectClass *klass, void *data)
|
|
|
|
|
{
|
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
ICSStateClass *isc = ICS_CLASS(klass);
|
2019-09-26 06:11:23 +02:00
|
|
|
SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
|
2019-09-24 07:51:55 +02:00
|
|
|
|
|
|
|
|
device_class_set_parent_realize(dc, ics_spapr_realize,
|
|
|
|
|
&isc->parent_realize);
|
2019-09-26 15:58:36 +02:00
|
|
|
sicc->activate = xics_spapr_activate;
|
|
|
|
|
sicc->deactivate = xics_spapr_deactivate;
|
2019-09-26 06:11:23 +02:00
|
|
|
sicc->cpu_intc_create = xics_spapr_cpu_intc_create;
|
2019-10-22 18:38:10 +02:00
|
|
|
sicc->cpu_intc_reset = xics_spapr_cpu_intc_reset;
|
2019-10-24 16:27:22 +02:00
|
|
|
sicc->cpu_intc_destroy = xics_spapr_cpu_intc_destroy;
|
2019-09-26 06:31:13 +02:00
|
|
|
sicc->claim_irq = xics_spapr_claim_irq;
|
|
|
|
|
sicc->free_irq = xics_spapr_free_irq;
|
2019-09-26 08:09:46 +02:00
|
|
|
sicc->set_irq = xics_spapr_set_irq;
|
2019-09-26 08:12:05 +02:00
|
|
|
sicc->print_info = xics_spapr_print_info;
|
2019-09-30 04:35:06 +02:00
|
|
|
sicc->dt = xics_spapr_dt;
|
2019-09-27 02:53:53 +02:00
|
|
|
sicc->post_load = xics_spapr_post_load;
|
2019-09-24 07:51:55 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const TypeInfo ics_spapr_info = {
|
|
|
|
|
.name = TYPE_ICS_SPAPR,
|
|
|
|
|
.parent = TYPE_ICS,
|
|
|
|
|
.class_init = ics_spapr_class_init,
|
2019-09-24 08:25:08 +02:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
|
{ TYPE_SPAPR_INTC },
|
|
|
|
|
{ }
|
|
|
|
|
},
|
2019-09-24 07:51:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void xics_spapr_register_types(void)
|
|
|
|
|
{
|
|
|
|
|
type_register_static(&ics_spapr_info);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
type_init(xics_spapr_register_types)
|