2012-02-16 10:56:05 +01:00
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/*
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* Samsung exynos4210 SoC emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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* Maksim Kozlov <m.kozlov@samsung.com>
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* Evgeny Voevodin <e.voevodin@samsung.com>
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* Igor Mitsyanko <i.mitsyanko@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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2015-12-07 17:23:45 +01:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2016-01-19 21:51:44 +01:00
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#include "qemu-common.h"
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2017-02-28 13:08:20 +01:00
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#include "qemu/log.h"
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2016-01-19 21:51:44 +01:00
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#include "cpu.h"
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2017-06-13 15:56:58 +02:00
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#include "hw/cpu/a9mpcore.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/boards.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
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2019-05-23 15:47:43 +02:00
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#include "hw/arm/boot.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/loader.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/arm/exynos4210.h"
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2017-09-04 16:21:53 +02:00
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#include "hw/sd/sdhci.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/usb/hcd-ehci.h"
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2012-02-16 10:56:05 +01:00
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#define EXYNOS4210_CHIPID_ADDR 0x10000000
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2012-02-16 10:56:05 +01:00
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/* PWM */
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#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
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2012-07-04 12:43:32 +02:00
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/* RTC */
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#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
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2012-02-16 10:56:05 +01:00
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/* MCT */
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#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
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2012-07-18 10:18:34 +02:00
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/* I2C */
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#define EXYNOS4210_I2C_SHIFT 0x00010000
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#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
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/* Interrupt Group of External Interrupt Combiner for I2C */
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#define EXYNOS4210_I2C_INTG 27
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#define EXYNOS4210_HDMI_INTG 16
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2012-02-16 10:56:05 +01:00
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/* UART's definitions */
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#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
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#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
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#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
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#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
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#define EXYNOS4210_UART0_FIFO_SIZE 256
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#define EXYNOS4210_UART1_FIFO_SIZE 64
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#define EXYNOS4210_UART2_FIFO_SIZE 16
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#define EXYNOS4210_UART3_FIFO_SIZE 16
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/* Interrupt Group of External Interrupt Combiner for UART */
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#define EXYNOS4210_UART_INT_GRP 26
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2012-02-16 10:56:05 +01:00
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/* External GIC */
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#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
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#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
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/* Combiner */
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#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
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#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
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hw/arm/exynos: Add generic SDHCI devices
Exynos4210 has four SD/MMC controllers supporting:
- SD Standard Host Specification Version 2.0,
- MMC Specification Version 4.3,
- SDIO Card Specification Version 2.0,
- DMA and ADMA.
Add emulation of SDHCI devices which allows accessing storage through SD
cards. Differences from real hardware:
- Devices are shipped with eMMC memory, not SD card.
- The Exynos4210 SDHCI has few more registers, e.g. for
controlling the clocks, additional status (0x80, 0x84, 0x8c). These
are not implemented.
Testing on smdkc210 machine with "-drive file=FILE,if=sd,bus=0,index=2".
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Message-id: 20170422190709.8676-1-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-22 21:07:09 +02:00
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/* SD/MMC host controllers */
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#define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080
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#define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000
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#define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \
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0x00010000 * (n))
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#define EXYNOS4210_SDHCI_NUMBER 4
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2012-02-16 10:56:05 +01:00
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/* PMU SFR base address */
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#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
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2017-02-28 13:08:20 +01:00
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/* Clock controller SFR base address */
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#define EXYNOS4210_CLK_BASE_ADDR 0x10030000
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2017-07-11 12:21:26 +02:00
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/* PRNG/HASH SFR base address */
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#define EXYNOS4210_RNG_BASE_ADDR 0x10830400
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2012-02-16 10:56:06 +01:00
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/* Display controllers (FIMD) */
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#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
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2012-12-16 04:49:46 +01:00
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/* EHCI */
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#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
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hw/arm/exynos4210: Add DMA support for the Exynos4210
QEMU already supports pl330. Instantiate it for Exynos4210.
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
/ {
soc: soc {
amba {
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
};
};
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-23 15:47:44 +02:00
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/* DMA */
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#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
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#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
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#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
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2012-02-16 10:56:05 +01:00
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static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
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0x09, 0x00, 0x00, 0x00 };
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2013-06-03 18:17:46 +02:00
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static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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assert(offset < sizeof(chipid_and_omr));
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return chipid_and_omr[offset];
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}
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static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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return;
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}
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static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
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.read = exynos4210_chipid_and_omr_read,
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.write = exynos4210_chipid_and_omr_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.max_access_size = 1,
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}
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};
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2012-05-14 00:08:10 +02:00
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void exynos4210_write_secondary(ARMCPU *cpu,
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2012-04-13 13:39:06 +02:00
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const struct arm_boot_info *info)
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{
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int n;
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uint32_t smpboot[] = {
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2012-12-11 12:30:37 +01:00
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0xe59f3034, /* ldr r3, External gic_cpu_if */
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0xe59f2034, /* ldr r2, Internal gic_cpu_if */
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0xe59f0034, /* ldr r0, startaddr */
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2012-04-13 13:39:06 +02:00
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0xe3a01001, /* mov r1, #1 */
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0xe5821000, /* str r1, [r2] */
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0xe5831000, /* str r1, [r3] */
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2012-12-11 12:30:37 +01:00
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0xe3a010ff, /* mov r1, #0xff */
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0xe5821004, /* str r1, [r2, #4] */
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0xe5831004, /* str r1, [r3, #4] */
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0xf57ff04f, /* dsb */
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2012-04-13 13:39:06 +02:00
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0xe320f003, /* wfi */
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0xe5901000, /* ldr r1, [r0] */
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0xe1110001, /* tst r1, r1 */
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0x0afffffb, /* beq <wfi> */
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0xe12fff11, /* bx r1 */
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EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
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0, /* gic_cpu_if: base address of Internal GIC CPU interface */
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0 /* bootreg: Boot register address is held here */
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};
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smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
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smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
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for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
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smpboot[n] = tswap32(smpboot[n]);
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}
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rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
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info->smp_loader_start);
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}
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2017-02-28 13:08:20 +01:00
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static uint64_t exynos4210_calc_affinity(int cpu)
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{
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/* Exynos4210 has 0x9 as cluster ID */
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2018-03-23 15:32:02 +01:00
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return (0x9 << ARM_AFF1_SHIFT) | cpu;
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2017-02-28 13:08:20 +01:00
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}
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hw/arm/exynos4210: Add DMA support for the Exynos4210
QEMU already supports pl330. Instantiate it for Exynos4210.
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
/ {
soc: soc {
amba {
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
};
};
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-23 15:47:44 +02:00
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static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
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{
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SysBusDevice *busdev;
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DeviceState *dev;
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dev = qdev_create(NULL, "pl330");
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qdev_prop_set_uint8(dev, "num_periph_req", nreq);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, base);
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sysbus_connect_irq(busdev, 0, irq);
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}
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2019-05-23 15:47:44 +02:00
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static void exynos4210_realize(DeviceState *socdev, Error **errp)
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2012-02-16 10:56:05 +01:00
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{
|
2019-05-23 15:47:44 +02:00
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Exynos4210State *s = EXYNOS4210_SOC(socdev);
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MemoryRegion *system_mem = get_system_memory();
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2012-05-28 06:11:49 +02:00
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qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
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2012-02-16 10:56:05 +01:00
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SysBusDevice *busdev;
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2017-06-13 15:56:57 +02:00
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DeviceState *dev;
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int i, n;
|
2014-03-17 17:31:46 +01:00
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2012-02-16 10:56:05 +01:00
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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2017-09-13 18:04:57 +02:00
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Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
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2014-03-17 17:31:46 +01:00
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2014-12-16 00:09:51 +01:00
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/* By default A9 CPUs have EL3 enabled. This board does not currently
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* support EL3 so the CPU EL3 property is disabled before realization.
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*/
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if (object_property_find(cpuobj, "has_el3", NULL)) {
|
2015-09-11 15:04:45 +02:00
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object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
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2014-12-16 00:09:51 +01:00
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}
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2014-03-17 17:31:46 +01:00
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s->cpu[n] = ARM_CPU(cpuobj);
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2017-02-28 13:08:20 +01:00
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object_property_set_int(cpuobj, exynos4210_calc_affinity(n),
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"mp-affinity", &error_abort);
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2014-03-17 17:31:46 +01:00
|
|
|
object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
|
|
|
|
"reset-cbar", &error_abort);
|
2015-09-11 15:04:45 +02:00
|
|
|
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
|
2012-02-16 10:56:05 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/*** IRQs ***/
|
|
|
|
|
|
|
|
s->irq_table = exynos4210_init_irq(&s->irqs);
|
|
|
|
|
|
|
|
/* IRQ Gate */
|
2012-05-28 06:11:49 +02:00
|
|
|
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
|
|
|
|
dev = qdev_create(NULL, "exynos4210.irq_gate");
|
|
|
|
qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
/* Get IRQ Gate input in gate_irq */
|
|
|
|
for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
|
|
|
|
gate_irq[i][n] = qdev_get_gpio_in(dev, n);
|
|
|
|
}
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-05-28 06:11:49 +02:00
|
|
|
|
2013-08-20 15:54:28 +02:00
|
|
|
/* Connect IRQ Gate output to CPU's IRQ line */
|
|
|
|
sysbus_connect_irq(busdev, 0,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
|
2012-02-16 10:56:05 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Private memory region and Internal GIC */
|
2017-06-13 15:56:58 +02:00
|
|
|
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
|
2012-02-16 10:56:05 +01:00
|
|
|
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-02-16 10:56:05 +01:00
|
|
|
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
|
|
|
|
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
|
2012-05-28 06:11:49 +02:00
|
|
|
sysbus_connect_irq(busdev, n, gate_irq[n][0]);
|
2012-02-16 10:56:05 +01:00
|
|
|
}
|
|
|
|
for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
|
|
|
|
s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Cache controller */
|
|
|
|
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
|
|
|
|
|
|
|
|
/* External GIC */
|
|
|
|
dev = qdev_create(NULL, "exynos4210.gic");
|
|
|
|
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-02-16 10:56:05 +01:00
|
|
|
/* Map CPU interface */
|
|
|
|
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
|
|
|
|
/* Map Distributer interface */
|
|
|
|
sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
|
|
|
|
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
|
2012-05-28 06:11:49 +02:00
|
|
|
sysbus_connect_irq(busdev, n, gate_irq[n][1]);
|
2012-02-16 10:56:05 +01:00
|
|
|
}
|
|
|
|
for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
|
|
|
|
s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Internal Interrupt Combiner */
|
|
|
|
dev = qdev_create(NULL, "exynos4210.combiner");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-02-16 10:56:05 +01:00
|
|
|
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
|
|
|
|
sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
|
|
|
|
}
|
|
|
|
exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
|
|
|
|
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
|
|
|
|
|
|
|
|
/* External Interrupt Combiner */
|
|
|
|
dev = qdev_create(NULL, "exynos4210.combiner");
|
|
|
|
qdev_prop_set_uint32(dev, "external", 1);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-02-16 10:56:05 +01:00
|
|
|
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
|
|
|
|
sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
|
|
|
|
}
|
|
|
|
exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
|
|
|
|
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
|
|
|
|
|
|
|
|
/* Initialize board IRQs. */
|
|
|
|
exynos4210_init_board_irqs(&s->irqs);
|
|
|
|
|
|
|
|
/*** Memory ***/
|
|
|
|
|
|
|
|
/* Chip-ID and OMR */
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
|
2013-06-03 18:17:46 +02:00
|
|
|
NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
|
2012-02-16 10:56:05 +01:00
|
|
|
memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
|
|
|
|
&s->chipid_mem);
|
|
|
|
|
|
|
|
/* Internal ROM */
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
EXYNOS4210_IROM_SIZE, &error_fatal);
|
2012-02-16 10:56:05 +01:00
|
|
|
memory_region_set_readonly(&s->irom_mem, true);
|
|
|
|
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
|
|
|
|
&s->irom_mem);
|
|
|
|
/* mirror of iROM */
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
|
2012-02-16 10:56:05 +01:00
|
|
|
&s->irom_mem,
|
2012-07-04 12:43:32 +02:00
|
|
|
0,
|
2012-02-16 10:56:05 +01:00
|
|
|
EXYNOS4210_IROM_SIZE);
|
|
|
|
memory_region_set_readonly(&s->irom_alias_mem, true);
|
|
|
|
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
|
|
|
|
&s->irom_alias_mem);
|
|
|
|
|
|
|
|
/* Internal RAM */
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
EXYNOS4210_IRAM_SIZE, &error_fatal);
|
2012-02-16 10:56:05 +01:00
|
|
|
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
|
|
|
|
&s->iram_mem);
|
|
|
|
|
2012-02-16 10:56:05 +01:00
|
|
|
/* PMU.
|
|
|
|
* The only reason of existence at the moment is that secondary CPU boot
|
|
|
|
* loader uses PMU INFORM5 register as a holding pen.
|
|
|
|
*/
|
|
|
|
sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
|
|
|
|
|
2017-02-28 13:08:20 +01:00
|
|
|
sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
|
2017-07-11 12:21:26 +02:00
|
|
|
sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
|
2017-02-28 13:08:20 +01:00
|
|
|
|
2012-02-16 10:56:05 +01:00
|
|
|
/* PWM */
|
|
|
|
sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
|
|
|
|
s->irq_table[exynos4210_get_irq(22, 0)],
|
|
|
|
s->irq_table[exynos4210_get_irq(22, 1)],
|
|
|
|
s->irq_table[exynos4210_get_irq(22, 2)],
|
|
|
|
s->irq_table[exynos4210_get_irq(22, 3)],
|
|
|
|
s->irq_table[exynos4210_get_irq(22, 4)],
|
|
|
|
NULL);
|
2012-07-04 12:43:32 +02:00
|
|
|
/* RTC */
|
|
|
|
sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
|
|
|
|
s->irq_table[exynos4210_get_irq(23, 0)],
|
|
|
|
s->irq_table[exynos4210_get_irq(23, 1)],
|
|
|
|
NULL);
|
2012-02-16 10:56:05 +01:00
|
|
|
|
2012-02-16 10:56:05 +01:00
|
|
|
/* Multi Core Timer */
|
|
|
|
dev = qdev_create(NULL, "exynos4210.mct");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-02-16 10:56:05 +01:00
|
|
|
for (n = 0; n < 4; n++) {
|
|
|
|
/* Connect global timer interrupts to Combiner gpio_in */
|
|
|
|
sysbus_connect_irq(busdev, n,
|
|
|
|
s->irq_table[exynos4210_get_irq(1, 4 + n)]);
|
|
|
|
}
|
|
|
|
/* Connect local timer interrupts to Combiner gpio_in */
|
|
|
|
sysbus_connect_irq(busdev, 4,
|
|
|
|
s->irq_table[exynos4210_get_irq(51, 0)]);
|
|
|
|
sysbus_connect_irq(busdev, 5,
|
|
|
|
s->irq_table[exynos4210_get_irq(35, 3)]);
|
|
|
|
sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
|
|
|
|
|
2012-07-18 10:18:34 +02:00
|
|
|
/*** I2C ***/
|
|
|
|
for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
|
|
|
|
uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
|
|
|
|
qemu_irq i2c_irq;
|
|
|
|
|
|
|
|
if (n < 8) {
|
|
|
|
i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
|
|
|
|
} else {
|
|
|
|
i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
|
|
|
|
}
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "exynos4210.i2c");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-07-18 10:18:34 +02:00
|
|
|
sysbus_connect_irq(busdev, 0, i2c_irq);
|
|
|
|
sysbus_mmio_map(busdev, 0, addr);
|
2013-08-03 00:18:51 +02:00
|
|
|
s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
|
2012-07-18 10:18:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-02-16 10:56:05 +01:00
|
|
|
/*** UARTs ***/
|
|
|
|
exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
|
2018-09-25 15:02:30 +02:00
|
|
|
EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
|
2012-02-16 10:56:05 +01:00
|
|
|
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
|
|
|
|
|
|
|
|
exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
|
2018-09-25 15:02:30 +02:00
|
|
|
EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
|
2012-02-16 10:56:05 +01:00
|
|
|
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
|
|
|
|
|
|
|
|
exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
|
2018-09-25 15:02:30 +02:00
|
|
|
EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
|
2012-02-16 10:56:05 +01:00
|
|
|
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
|
|
|
|
|
|
|
|
exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
|
2018-09-25 15:02:30 +02:00
|
|
|
EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
|
2012-02-16 10:56:05 +01:00
|
|
|
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
|
|
|
|
|
hw/arm/exynos: Add generic SDHCI devices
Exynos4210 has four SD/MMC controllers supporting:
- SD Standard Host Specification Version 2.0,
- MMC Specification Version 4.3,
- SDIO Card Specification Version 2.0,
- DMA and ADMA.
Add emulation of SDHCI devices which allows accessing storage through SD
cards. Differences from real hardware:
- Devices are shipped with eMMC memory, not SD card.
- The Exynos4210 SDHCI has few more registers, e.g. for
controlling the clocks, additional status (0x80, 0x84, 0x8c). These
are not implemented.
Testing on smdkc210 machine with "-drive file=FILE,if=sd,bus=0,index=2".
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Message-id: 20170422190709.8676-1-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-22 21:07:09 +02:00
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/*** SD/MMC host controllers ***/
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for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) {
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DeviceState *carddev;
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BlockBackend *blk;
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DriveInfo *di;
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2018-02-08 17:48:03 +01:00
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/* Compatible with:
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* - SD Host Controller Specification Version 2.0
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* - SDIO Specification Version 2.0
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* - MMC Specification Version 4.3
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* - SDMA
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* - ADMA2
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*
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* As this part of the Exynos4210 is not publically available,
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* we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
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* public datasheet which is very similar (implementing
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* MMC Specification Version 4.0 being the only difference noted)
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*/
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2017-09-04 16:21:53 +02:00
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dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
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2018-02-08 17:48:02 +01:00
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qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
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hw/arm/exynos: Add generic SDHCI devices
Exynos4210 has four SD/MMC controllers supporting:
- SD Standard Host Specification Version 2.0,
- MMC Specification Version 4.3,
- SDIO Card Specification Version 2.0,
- DMA and ADMA.
Add emulation of SDHCI devices which allows accessing storage through SD
cards. Differences from real hardware:
- Devices are shipped with eMMC memory, not SD card.
- The Exynos4210 SDHCI has few more registers, e.g. for
controlling the clocks, additional status (0x80, 0x84, 0x8c). These
are not implemented.
Testing on smdkc210 machine with "-drive file=FILE,if=sd,bus=0,index=2".
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Message-id: 20170422190709.8676-1-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-22 21:07:09 +02:00
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
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sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
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di = drive_get(IF_SD, 0, n);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
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qdev_prop_set_drive(carddev, "drive", blk, &error_abort);
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qdev_init_nofail(carddev);
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}
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2012-02-16 10:56:06 +01:00
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/*** Display controller (FIMD) ***/
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sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
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s->irq_table[exynos4210_get_irq(11, 0)],
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s->irq_table[exynos4210_get_irq(11, 1)],
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s->irq_table[exynos4210_get_irq(11, 2)],
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NULL);
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2012-12-16 04:49:46 +01:00
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sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
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s->irq_table[exynos4210_get_irq(28, 3)]);
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hw/arm/exynos4210: Add DMA support for the Exynos4210
QEMU already supports pl330. Instantiate it for Exynos4210.
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
/ {
soc: soc {
amba {
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
};
};
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-23 15:47:44 +02:00
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/*** DMA controllers ***/
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pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
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qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
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pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
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qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
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pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
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qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
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2019-05-23 15:47:44 +02:00
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}
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static void exynos4210_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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hw/arm/exynos4210: Add DMA support for the Exynos4210
QEMU already supports pl330. Instantiate it for Exynos4210.
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
/ {
soc: soc {
amba {
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
};
};
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-23 15:47:44 +02:00
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2019-05-23 15:47:44 +02:00
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dc->realize = exynos4210_realize;
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2012-02-16 10:56:05 +01:00
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}
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2019-05-23 15:47:44 +02:00
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static const TypeInfo exynos4210_info = {
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.name = TYPE_EXYNOS4210_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Exynos4210State),
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.class_init = exynos4210_class_init,
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};
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static void exynos4210_register_types(void)
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{
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type_register_static(&exynos4210_info);
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}
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type_init(exynos4210_register_types)
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