289 lines
8.4 KiB
C
289 lines
8.4 KiB
C
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/*
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* BCM2835 SPI Master Controller
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*
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* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/fifo8.h"
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#include "hw/ssi/bcm2835_spi.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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static void bcm2835_spi_update_int(BCM2835SPIState *s)
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{
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int do_interrupt = 0;
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/* Interrupt on DONE */
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if (s->cs & BCM2835_SPI_CS_INTD && s->cs & BCM2835_SPI_CS_DONE) {
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do_interrupt = 1;
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}
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/* Interrupt on RXR */
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if (s->cs & BCM2835_SPI_CS_INTR && s->cs & BCM2835_SPI_CS_RXR) {
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do_interrupt = 1;
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}
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qemu_set_irq(s->irq, do_interrupt);
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}
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static void bcm2835_spi_update_rx_flags(BCM2835SPIState *s)
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{
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/* Set RXD if RX FIFO is non empty */
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if (!fifo8_is_empty(&s->rx_fifo)) {
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s->cs |= BCM2835_SPI_CS_RXD;
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} else {
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s->cs &= ~BCM2835_SPI_CS_RXD;
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}
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/* Set RXF if RX FIFO is full */
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if (fifo8_is_full(&s->rx_fifo)) {
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s->cs |= BCM2835_SPI_CS_RXF;
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} else {
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s->cs &= ~BCM2835_SPI_CS_RXF;
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}
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/* Set RXR if RX FIFO is 3/4th used or above */
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if (fifo8_num_used(&s->rx_fifo) >= FIFO_SIZE_3_4) {
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s->cs |= BCM2835_SPI_CS_RXR;
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} else {
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s->cs &= ~BCM2835_SPI_CS_RXR;
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}
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}
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static void bcm2835_spi_update_tx_flags(BCM2835SPIState *s)
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{
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/* Set TXD if TX FIFO is not full */
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if (fifo8_is_full(&s->tx_fifo)) {
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s->cs &= ~BCM2835_SPI_CS_TXD;
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} else {
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s->cs |= BCM2835_SPI_CS_TXD;
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}
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/* Set DONE if in TA mode and TX FIFO is empty */
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if (fifo8_is_empty(&s->tx_fifo) && s->cs & BCM2835_SPI_CS_TA) {
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s->cs |= BCM2835_SPI_CS_DONE;
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} else {
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s->cs &= ~BCM2835_SPI_CS_DONE;
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}
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}
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static void bcm2835_spi_flush_tx_fifo(BCM2835SPIState *s)
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{
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uint8_t tx_byte, rx_byte;
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while (!fifo8_is_empty(&s->tx_fifo) && !fifo8_is_full(&s->rx_fifo)) {
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tx_byte = fifo8_pop(&s->tx_fifo);
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rx_byte = ssi_transfer(s->bus, tx_byte);
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fifo8_push(&s->rx_fifo, rx_byte);
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}
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bcm2835_spi_update_tx_flags(s);
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bcm2835_spi_update_rx_flags(s);
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}
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static uint64_t bcm2835_spi_read(void *opaque, hwaddr addr, unsigned size)
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{
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BCM2835SPIState *s = opaque;
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uint32_t readval = 0;
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switch (addr) {
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case BCM2835_SPI_CS:
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readval = s->cs & 0xffffffff;
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break;
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case BCM2835_SPI_FIFO:
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bcm2835_spi_flush_tx_fifo(s);
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if (s->cs & BCM2835_SPI_CS_RXD) {
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readval = fifo8_pop(&s->rx_fifo);
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bcm2835_spi_update_rx_flags(s);
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}
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bcm2835_spi_update_int(s);
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break;
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case BCM2835_SPI_CLK:
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readval = s->clk & 0xffff;
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break;
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case BCM2835_SPI_DLEN:
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readval = s->dlen & 0xffff;
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break;
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case BCM2835_SPI_LTOH:
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readval = s->ltoh & 0xf;
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break;
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case BCM2835_SPI_DC:
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readval = s->dc & 0xffffffff;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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return readval;
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}
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static void bcm2835_spi_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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BCM2835SPIState *s = opaque;
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switch (addr) {
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case BCM2835_SPI_CS:
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s->cs = (value & ~RO_MASK) | (s->cs & RO_MASK);
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if (!(s->cs & BCM2835_SPI_CS_TA)) {
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/* Clear DONE and RXR if TA is off */
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s->cs &= ~(BCM2835_SPI_CS_DONE);
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s->cs &= ~(BCM2835_SPI_CS_RXR);
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}
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/* Clear RX FIFO */
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if (s->cs & BCM2835_SPI_CLEAR_RX) {
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fifo8_reset(&s->rx_fifo);
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bcm2835_spi_update_rx_flags(s);
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}
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/* Clear TX FIFO*/
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if (s->cs & BCM2835_SPI_CLEAR_TX) {
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fifo8_reset(&s->tx_fifo);
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bcm2835_spi_update_tx_flags(s);
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}
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/* Set Transfer Active */
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if (s->cs & BCM2835_SPI_CS_TA) {
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bcm2835_spi_update_tx_flags(s);
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}
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if (s->cs & BCM2835_SPI_CS_DMAEN) {
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"DMA not supported\n", __func__);
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}
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if (s->cs & BCM2835_SPI_CS_LEN) {
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"LoSSI not supported\n", __func__);
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}
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bcm2835_spi_update_int(s);
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break;
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case BCM2835_SPI_FIFO:
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/*
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* According to documentation, writes to FIFO without TA controls
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* CS and DLEN registers. This is supposed to be used in DMA mode
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* which is currently unimplemented. Moreover, Linux does not make
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* use of this and directly modifies the CS and DLEN registers.
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*/
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if (s->cs & BCM2835_SPI_CS_TA) {
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if (s->cs & BCM2835_SPI_CS_TXD) {
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fifo8_push(&s->tx_fifo, value & 0xff);
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bcm2835_spi_update_tx_flags(s);
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}
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bcm2835_spi_flush_tx_fifo(s);
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bcm2835_spi_update_int(s);
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}
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break;
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case BCM2835_SPI_CLK:
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s->clk = value & 0xffff;
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break;
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case BCM2835_SPI_DLEN:
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s->dlen = value & 0xffff;
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break;
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case BCM2835_SPI_LTOH:
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s->ltoh = value & 0xf;
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break;
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case BCM2835_SPI_DC:
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s->dc = value & 0xffffffff;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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}
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static const MemoryRegionOps bcm2835_spi_ops = {
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.read = bcm2835_spi_read,
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.write = bcm2835_spi_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void bcm2835_spi_realize(DeviceState *dev, Error **errp)
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{
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BCM2835SPIState *s = BCM2835_SPI(dev);
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s->bus = ssi_create_bus(dev, "spi");
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memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_spi_ops, s,
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TYPE_BCM2835_SPI, 0x18);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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fifo8_create(&s->tx_fifo, FIFO_SIZE);
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fifo8_create(&s->rx_fifo, FIFO_SIZE);
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}
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static void bcm2835_spi_reset(DeviceState *dev)
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{
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BCM2835SPIState *s = BCM2835_SPI(dev);
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fifo8_reset(&s->tx_fifo);
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fifo8_reset(&s->rx_fifo);
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/* Reset values according to BCM2835 Peripheral Documentation */
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s->cs = BCM2835_SPI_CS_TXD | BCM2835_SPI_CS_REN;
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s->clk = 0;
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s->dlen = 0;
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s->ltoh = 0x1;
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s->dc = 0x30201020;
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}
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static const VMStateDescription vmstate_bcm2835_spi = {
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.name = TYPE_BCM2835_SPI,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_FIFO8(tx_fifo, BCM2835SPIState),
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VMSTATE_FIFO8(rx_fifo, BCM2835SPIState),
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VMSTATE_UINT32(cs, BCM2835SPIState),
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VMSTATE_UINT32(clk, BCM2835SPIState),
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VMSTATE_UINT32(dlen, BCM2835SPIState),
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VMSTATE_UINT32(ltoh, BCM2835SPIState),
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VMSTATE_UINT32(dc, BCM2835SPIState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void bcm2835_spi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = bcm2835_spi_reset;
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dc->realize = bcm2835_spi_realize;
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dc->vmsd = &vmstate_bcm2835_spi;
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}
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static const TypeInfo bcm2835_spi_info = {
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.name = TYPE_BCM2835_SPI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2835SPIState),
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.class_init = bcm2835_spi_class_init,
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};
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static void bcm2835_spi_register_types(void)
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{
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type_register_static(&bcm2835_spi_info);
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}
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type_init(bcm2835_spi_register_types)
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