2009-02-05 22:23:50 +01:00
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/*
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* DMA helper functions
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*
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* Copyright (c) 2009 Red Hat
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*
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* This work is licensed under the terms of the GNU General Public License
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* (GNU GPL), version 2 or later.
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*/
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2016-01-29 18:50:05 +01:00
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#include "qemu/osdep.h"
|
2014-10-07 13:59:18 +02:00
|
|
|
#include "sysemu/block-backend.h"
|
2012-12-17 18:20:04 +01:00
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#include "sysemu/dma.h"
|
2017-01-25 17:14:15 +01:00
|
|
|
#include "trace-root.h"
|
2012-12-17 18:20:00 +01:00
|
|
|
#include "qemu/thread.h"
|
2013-08-21 17:02:47 +02:00
|
|
|
#include "qemu/main-loop.h"
|
2009-02-05 22:23:50 +01:00
|
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|
|
2012-06-27 06:50:43 +02:00
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|
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/* #define DEBUG_IOMMU */
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|
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|
2013-04-10 18:15:49 +02:00
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|
|
int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
|
iommu: Add universal DMA helper functions
Not that long ago, every device implementation using DMA directly
accessed guest memory using cpu_physical_memory_*(). This meant that
adding support for a guest visible IOMMU would require changing every
one of these devices to go through IOMMU translation.
Shortly before qemu 1.0, I made a start on fixing this by providing
helper functions for PCI DMA. These are currently just stubs which
call the direct access functions, but mean that an IOMMU can be
implemented in one place, rather than for every PCI device.
Clearly, this doesn't help for non PCI devices, which could also be
IOMMU translated on some platforms. It is also problematic for the
devices which have both PCI and non-PCI version (e.g. OHCI, AHCI) - we
cannot use the the pci_dma_*() functions, because they assume the
presence of a PCIDevice, but we don't want to have to check between
pci_dma_*() and cpu_physical_memory_*() every time we do a DMA in the
device code.
This patch makes the first step on addressing both these problems, by
introducing new (stub) dma helper functions which can be used for any
DMA capable device.
These dma functions take a DMAContext *, a new (currently empty)
variable describing the DMA address space in which the operation is to
take place. NULL indicates untranslated DMA directly into guest
physical address space. The intention is that in future non-NULL
values will given information about any necessary IOMMU translation.
DMA using devices must obtain a DMAContext (or, potentially, contexts)
from their bus or platform. For now this patch just converts the PCI
wrappers to be implemented in terms of the universal wrappers,
converting other drivers can take place over time.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-27 06:50:38 +02:00
|
|
|
{
|
2013-04-10 18:15:49 +02:00
|
|
|
dma_barrier(as, DMA_DIRECTION_FROM_DEVICE);
|
2013-04-10 17:49:04 +02:00
|
|
|
|
iommu: Add universal DMA helper functions
Not that long ago, every device implementation using DMA directly
accessed guest memory using cpu_physical_memory_*(). This meant that
adding support for a guest visible IOMMU would require changing every
one of these devices to go through IOMMU translation.
Shortly before qemu 1.0, I made a start on fixing this by providing
helper functions for PCI DMA. These are currently just stubs which
call the direct access functions, but mean that an IOMMU can be
implemented in one place, rather than for every PCI device.
Clearly, this doesn't help for non PCI devices, which could also be
IOMMU translated on some platforms. It is also problematic for the
devices which have both PCI and non-PCI version (e.g. OHCI, AHCI) - we
cannot use the the pci_dma_*() functions, because they assume the
presence of a PCIDevice, but we don't want to have to check between
pci_dma_*() and cpu_physical_memory_*() every time we do a DMA in the
device code.
This patch makes the first step on addressing both these problems, by
introducing new (stub) dma helper functions which can be used for any
DMA capable device.
These dma functions take a DMAContext *, a new (currently empty)
variable describing the DMA address space in which the operation is to
take place. NULL indicates untranslated DMA directly into guest
physical address space. The intention is that in future non-NULL
values will given information about any necessary IOMMU translation.
DMA using devices must obtain a DMAContext (or, potentially, contexts)
from their bus or platform. For now this patch just converts the PCI
wrappers to be implemented in terms of the universal wrappers,
converting other drivers can take place over time.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-27 06:50:38 +02:00
|
|
|
#define FILLBUF_SIZE 512
|
|
|
|
uint8_t fillbuf[FILLBUF_SIZE];
|
|
|
|
int l;
|
2013-04-10 17:49:04 +02:00
|
|
|
bool error = false;
|
iommu: Add universal DMA helper functions
Not that long ago, every device implementation using DMA directly
accessed guest memory using cpu_physical_memory_*(). This meant that
adding support for a guest visible IOMMU would require changing every
one of these devices to go through IOMMU translation.
Shortly before qemu 1.0, I made a start on fixing this by providing
helper functions for PCI DMA. These are currently just stubs which
call the direct access functions, but mean that an IOMMU can be
implemented in one place, rather than for every PCI device.
Clearly, this doesn't help for non PCI devices, which could also be
IOMMU translated on some platforms. It is also problematic for the
devices which have both PCI and non-PCI version (e.g. OHCI, AHCI) - we
cannot use the the pci_dma_*() functions, because they assume the
presence of a PCIDevice, but we don't want to have to check between
pci_dma_*() and cpu_physical_memory_*() every time we do a DMA in the
device code.
This patch makes the first step on addressing both these problems, by
introducing new (stub) dma helper functions which can be used for any
DMA capable device.
These dma functions take a DMAContext *, a new (currently empty)
variable describing the DMA address space in which the operation is to
take place. NULL indicates untranslated DMA directly into guest
physical address space. The intention is that in future non-NULL
values will given information about any necessary IOMMU translation.
DMA using devices must obtain a DMAContext (or, potentially, contexts)
from their bus or platform. For now this patch just converts the PCI
wrappers to be implemented in terms of the universal wrappers,
converting other drivers can take place over time.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-27 06:50:38 +02:00
|
|
|
|
|
|
|
memset(fillbuf, c, FILLBUF_SIZE);
|
|
|
|
while (len > 0) {
|
|
|
|
l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
|
2015-04-26 17:49:24 +02:00
|
|
|
error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
|
|
|
|
fillbuf, l, true);
|
2012-08-14 09:41:47 +02:00
|
|
|
len -= l;
|
|
|
|
addr += l;
|
iommu: Add universal DMA helper functions
Not that long ago, every device implementation using DMA directly
accessed guest memory using cpu_physical_memory_*(). This meant that
adding support for a guest visible IOMMU would require changing every
one of these devices to go through IOMMU translation.
Shortly before qemu 1.0, I made a start on fixing this by providing
helper functions for PCI DMA. These are currently just stubs which
call the direct access functions, but mean that an IOMMU can be
implemented in one place, rather than for every PCI device.
Clearly, this doesn't help for non PCI devices, which could also be
IOMMU translated on some platforms. It is also problematic for the
devices which have both PCI and non-PCI version (e.g. OHCI, AHCI) - we
cannot use the the pci_dma_*() functions, because they assume the
presence of a PCIDevice, but we don't want to have to check between
pci_dma_*() and cpu_physical_memory_*() every time we do a DMA in the
device code.
This patch makes the first step on addressing both these problems, by
introducing new (stub) dma helper functions which can be used for any
DMA capable device.
These dma functions take a DMAContext *, a new (currently empty)
variable describing the DMA address space in which the operation is to
take place. NULL indicates untranslated DMA directly into guest
physical address space. The intention is that in future non-NULL
values will given information about any necessary IOMMU translation.
DMA using devices must obtain a DMAContext (or, potentially, contexts)
from their bus or platform. For now this patch just converts the PCI
wrappers to be implemented in terms of the universal wrappers,
converting other drivers can take place over time.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-27 06:50:38 +02:00
|
|
|
}
|
2012-06-27 06:50:43 +02:00
|
|
|
|
2013-04-10 17:49:04 +02:00
|
|
|
return error;
|
iommu: Add universal DMA helper functions
Not that long ago, every device implementation using DMA directly
accessed guest memory using cpu_physical_memory_*(). This meant that
adding support for a guest visible IOMMU would require changing every
one of these devices to go through IOMMU translation.
Shortly before qemu 1.0, I made a start on fixing this by providing
helper functions for PCI DMA. These are currently just stubs which
call the direct access functions, but mean that an IOMMU can be
implemented in one place, rather than for every PCI device.
Clearly, this doesn't help for non PCI devices, which could also be
IOMMU translated on some platforms. It is also problematic for the
devices which have both PCI and non-PCI version (e.g. OHCI, AHCI) - we
cannot use the the pci_dma_*() functions, because they assume the
presence of a PCIDevice, but we don't want to have to check between
pci_dma_*() and cpu_physical_memory_*() every time we do a DMA in the
device code.
This patch makes the first step on addressing both these problems, by
introducing new (stub) dma helper functions which can be used for any
DMA capable device.
These dma functions take a DMAContext *, a new (currently empty)
variable describing the DMA address space in which the operation is to
take place. NULL indicates untranslated DMA directly into guest
physical address space. The intention is that in future non-NULL
values will given information about any necessary IOMMU translation.
DMA using devices must obtain a DMAContext (or, potentially, contexts)
from their bus or platform. For now this patch just converts the PCI
wrappers to be implemented in terms of the universal wrappers,
converting other drivers can take place over time.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-27 06:50:38 +02:00
|
|
|
}
|
|
|
|
|
2013-06-03 14:17:19 +02:00
|
|
|
void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
|
|
|
|
AddressSpace *as)
|
2009-02-05 22:23:50 +01:00
|
|
|
{
|
2011-08-21 05:09:37 +02:00
|
|
|
qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
|
2009-02-05 22:23:50 +01:00
|
|
|
qsg->nsg = 0;
|
|
|
|
qsg->nalloc = alloc_hint;
|
|
|
|
qsg->size = 0;
|
2013-04-10 18:15:49 +02:00
|
|
|
qsg->as = as;
|
2013-06-03 14:17:19 +02:00
|
|
|
qsg->dev = dev;
|
|
|
|
object_ref(OBJECT(dev));
|
2009-02-05 22:23:50 +01:00
|
|
|
}
|
|
|
|
|
2011-10-31 07:06:46 +01:00
|
|
|
void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
|
2009-02-05 22:23:50 +01:00
|
|
|
{
|
|
|
|
if (qsg->nsg == qsg->nalloc) {
|
|
|
|
qsg->nalloc = 2 * qsg->nalloc + 1;
|
2011-08-21 05:09:37 +02:00
|
|
|
qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
|
2009-02-05 22:23:50 +01:00
|
|
|
}
|
|
|
|
qsg->sg[qsg->nsg].base = base;
|
|
|
|
qsg->sg[qsg->nsg].len = len;
|
|
|
|
qsg->size += len;
|
|
|
|
++qsg->nsg;
|
|
|
|
}
|
|
|
|
|
|
|
|
void qemu_sglist_destroy(QEMUSGList *qsg)
|
|
|
|
{
|
2013-06-03 14:17:19 +02:00
|
|
|
object_unref(OBJECT(qsg->dev));
|
2011-08-21 05:09:37 +02:00
|
|
|
g_free(qsg->sg);
|
2012-08-03 21:57:10 +02:00
|
|
|
memset(qsg, 0, sizeof(*qsg));
|
2009-02-05 22:23:50 +01:00
|
|
|
}
|
|
|
|
|
2009-02-05 22:23:58 +01:00
|
|
|
typedef struct {
|
2014-10-07 13:59:14 +02:00
|
|
|
BlockAIOCB common;
|
2016-05-23 14:54:06 +02:00
|
|
|
AioContext *ctx;
|
2014-10-07 13:59:14 +02:00
|
|
|
BlockAIOCB *acb;
|
2009-02-05 22:23:58 +01:00
|
|
|
QEMUSGList *sg;
|
2016-10-27 22:29:13 +02:00
|
|
|
uint32_t align;
|
2016-05-06 18:26:31 +02:00
|
|
|
uint64_t offset;
|
2012-03-27 04:42:23 +02:00
|
|
|
DMADirection dir;
|
2009-02-05 22:23:58 +01:00
|
|
|
int sg_cur_index;
|
2011-10-31 07:06:46 +01:00
|
|
|
dma_addr_t sg_cur_byte;
|
2009-02-05 22:23:58 +01:00
|
|
|
QEMUIOVector iov;
|
|
|
|
QEMUBH *bh;
|
2011-05-19 10:57:59 +02:00
|
|
|
DMAIOFunc *io_func;
|
2016-05-23 14:54:06 +02:00
|
|
|
void *io_func_opaque;
|
2009-03-20 19:26:16 +01:00
|
|
|
} DMAAIOCB;
|
2009-02-05 22:23:58 +01:00
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
static void dma_blk_cb(void *opaque, int ret);
|
2009-02-05 22:23:58 +01:00
|
|
|
|
|
|
|
static void reschedule_dma(void *opaque)
|
|
|
|
{
|
2009-03-20 19:26:16 +01:00
|
|
|
DMAAIOCB *dbs = (DMAAIOCB *)opaque;
|
2009-02-05 22:23:58 +01:00
|
|
|
|
|
|
|
qemu_bh_delete(dbs->bh);
|
|
|
|
dbs->bh = NULL;
|
2014-10-07 13:59:18 +02:00
|
|
|
dma_blk_cb(dbs, 0);
|
2009-02-05 22:23:58 +01:00
|
|
|
}
|
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
static void dma_blk_unmap(DMAAIOCB *dbs)
|
2009-02-05 22:23:58 +01:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < dbs->iov.niov; ++i) {
|
2013-04-10 18:15:49 +02:00
|
|
|
dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base,
|
2012-06-27 06:50:40 +02:00
|
|
|
dbs->iov.iov[i].iov_len, dbs->dir,
|
|
|
|
dbs->iov.iov[i].iov_len);
|
2009-02-05 22:23:58 +01:00
|
|
|
}
|
2011-09-16 16:40:02 +02:00
|
|
|
qemu_iovec_reset(&dbs->iov);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dma_complete(DMAAIOCB *dbs, int ret)
|
|
|
|
{
|
2011-11-24 12:15:28 +01:00
|
|
|
trace_dma_complete(dbs, ret, dbs->common.cb);
|
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
dma_blk_unmap(dbs);
|
2011-09-16 16:40:02 +02:00
|
|
|
if (dbs->common.cb) {
|
|
|
|
dbs->common.cb(dbs->common.opaque, ret);
|
|
|
|
}
|
|
|
|
qemu_iovec_destroy(&dbs->iov);
|
|
|
|
if (dbs->bh) {
|
|
|
|
qemu_bh_delete(dbs->bh);
|
|
|
|
dbs->bh = NULL;
|
|
|
|
}
|
2014-09-11 07:41:28 +02:00
|
|
|
qemu_aio_unref(dbs);
|
2009-03-28 17:11:25 +01:00
|
|
|
}
|
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
static void dma_blk_cb(void *opaque, int ret)
|
2009-03-28 17:11:25 +01:00
|
|
|
{
|
|
|
|
DMAAIOCB *dbs = (DMAAIOCB *)opaque;
|
2012-06-27 06:50:40 +02:00
|
|
|
dma_addr_t cur_addr, cur_len;
|
2009-03-28 17:11:25 +01:00
|
|
|
void *mem;
|
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
trace_dma_blk_cb(dbs, ret);
|
2011-11-24 12:15:28 +01:00
|
|
|
|
2009-03-28 17:11:25 +01:00
|
|
|
dbs->acb = NULL;
|
2016-05-06 18:26:31 +02:00
|
|
|
dbs->offset += dbs->iov.size;
|
2009-02-05 22:23:58 +01:00
|
|
|
|
|
|
|
if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
|
2011-09-16 16:40:02 +02:00
|
|
|
dma_complete(dbs, ret);
|
2009-02-05 22:23:58 +01:00
|
|
|
return;
|
|
|
|
}
|
2014-10-07 13:59:18 +02:00
|
|
|
dma_blk_unmap(dbs);
|
2009-02-05 22:23:58 +01:00
|
|
|
|
|
|
|
while (dbs->sg_cur_index < dbs->sg->nsg) {
|
|
|
|
cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
|
|
|
|
cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
|
2013-04-10 18:15:49 +02:00
|
|
|
mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir);
|
2009-02-05 22:23:58 +01:00
|
|
|
if (!mem)
|
|
|
|
break;
|
|
|
|
qemu_iovec_add(&dbs->iov, mem, cur_len);
|
|
|
|
dbs->sg_cur_byte += cur_len;
|
|
|
|
if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
|
|
|
|
dbs->sg_cur_byte = 0;
|
|
|
|
++dbs->sg_cur_index;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dbs->iov.size == 0) {
|
2011-11-24 12:15:28 +01:00
|
|
|
trace_dma_map_wait(dbs);
|
2016-05-23 14:54:06 +02:00
|
|
|
dbs->bh = aio_bh_new(dbs->ctx, reschedule_dma, dbs);
|
2015-03-16 10:03:37 +01:00
|
|
|
cpu_register_map_client(dbs->bh);
|
2009-02-05 22:23:58 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-10-27 22:29:13 +02:00
|
|
|
if (!QEMU_IS_ALIGNED(dbs->iov.size, dbs->align)) {
|
|
|
|
qemu_iovec_discard_back(&dbs->iov,
|
|
|
|
QEMU_ALIGN_DOWN(dbs->iov.size, dbs->align));
|
2014-07-09 19:17:30 +02:00
|
|
|
}
|
|
|
|
|
2017-02-13 14:52:31 +01:00
|
|
|
aio_context_acquire(dbs->ctx);
|
2016-05-23 14:54:06 +02:00
|
|
|
dbs->acb = dbs->io_func(dbs->offset, &dbs->iov,
|
|
|
|
dma_blk_cb, dbs, dbs->io_func_opaque);
|
2017-02-13 14:52:31 +01:00
|
|
|
aio_context_release(dbs->ctx);
|
2011-11-14 17:50:52 +01:00
|
|
|
assert(dbs->acb);
|
2009-02-05 22:23:58 +01:00
|
|
|
}
|
|
|
|
|
2014-10-07 13:59:14 +02:00
|
|
|
static void dma_aio_cancel(BlockAIOCB *acb)
|
2009-05-25 12:37:32 +02:00
|
|
|
{
|
|
|
|
DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
|
|
|
|
|
2011-11-24 12:15:28 +01:00
|
|
|
trace_dma_aio_cancel(dbs);
|
|
|
|
|
2009-05-25 12:37:32 +02:00
|
|
|
if (dbs->acb) {
|
2014-10-07 13:59:18 +02:00
|
|
|
blk_aio_cancel_async(dbs->acb);
|
2009-05-25 12:37:32 +02:00
|
|
|
}
|
2015-03-16 10:03:37 +01:00
|
|
|
if (dbs->bh) {
|
|
|
|
cpu_unregister_map_client(dbs->bh);
|
|
|
|
qemu_bh_delete(dbs->bh);
|
|
|
|
dbs->bh = NULL;
|
|
|
|
}
|
2009-05-25 12:37:32 +02:00
|
|
|
}
|
|
|
|
|
2016-06-20 21:36:57 +02:00
|
|
|
static AioContext *dma_get_aio_context(BlockAIOCB *acb)
|
|
|
|
{
|
|
|
|
DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
|
|
|
|
|
|
|
|
return dbs->ctx;
|
|
|
|
}
|
2014-09-11 07:41:14 +02:00
|
|
|
|
2012-10-31 16:34:37 +01:00
|
|
|
static const AIOCBInfo dma_aiocb_info = {
|
2009-05-25 12:37:32 +02:00
|
|
|
.aiocb_size = sizeof(DMAAIOCB),
|
2014-09-11 07:41:14 +02:00
|
|
|
.cancel_async = dma_aio_cancel,
|
2016-06-20 21:36:57 +02:00
|
|
|
.get_aio_context = dma_get_aio_context,
|
2009-05-25 12:37:32 +02:00
|
|
|
};
|
|
|
|
|
2016-05-23 14:54:06 +02:00
|
|
|
BlockAIOCB *dma_blk_io(AioContext *ctx,
|
2016-10-27 22:29:13 +02:00
|
|
|
QEMUSGList *sg, uint64_t offset, uint32_t align,
|
2016-05-23 14:54:06 +02:00
|
|
|
DMAIOFunc *io_func, void *io_func_opaque,
|
|
|
|
BlockCompletionFunc *cb,
|
2012-03-27 04:42:23 +02:00
|
|
|
void *opaque, DMADirection dir)
|
2009-02-05 22:23:58 +01:00
|
|
|
{
|
2016-05-23 14:54:06 +02:00
|
|
|
DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, NULL, cb, opaque);
|
2009-02-05 22:23:58 +01:00
|
|
|
|
2016-05-23 14:54:06 +02:00
|
|
|
trace_dma_blk_io(dbs, io_func_opaque, offset, (dir == DMA_DIRECTION_TO_DEVICE));
|
2011-11-24 12:15:28 +01:00
|
|
|
|
2009-03-20 19:26:16 +01:00
|
|
|
dbs->acb = NULL;
|
2009-02-05 22:23:58 +01:00
|
|
|
dbs->sg = sg;
|
2016-05-23 14:54:06 +02:00
|
|
|
dbs->ctx = ctx;
|
2016-05-23 14:54:05 +02:00
|
|
|
dbs->offset = offset;
|
2016-10-27 22:29:13 +02:00
|
|
|
dbs->align = align;
|
2009-02-05 22:23:58 +01:00
|
|
|
dbs->sg_cur_index = 0;
|
|
|
|
dbs->sg_cur_byte = 0;
|
2012-03-27 04:42:23 +02:00
|
|
|
dbs->dir = dir;
|
2011-05-19 10:57:59 +02:00
|
|
|
dbs->io_func = io_func;
|
2016-05-23 14:54:06 +02:00
|
|
|
dbs->io_func_opaque = io_func_opaque;
|
2009-02-05 22:23:58 +01:00
|
|
|
dbs->bh = NULL;
|
|
|
|
qemu_iovec_init(&dbs->iov, sg->nsg);
|
2014-10-07 13:59:18 +02:00
|
|
|
dma_blk_cb(dbs, 0);
|
2009-03-20 19:26:16 +01:00
|
|
|
return &dbs->common;
|
2009-02-05 22:23:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2016-05-23 14:54:06 +02:00
|
|
|
static
|
|
|
|
BlockAIOCB *dma_blk_read_io_func(int64_t offset, QEMUIOVector *iov,
|
|
|
|
BlockCompletionFunc *cb, void *cb_opaque,
|
|
|
|
void *opaque)
|
|
|
|
{
|
|
|
|
BlockBackend *blk = opaque;
|
|
|
|
return blk_aio_preadv(blk, offset, iov, 0, cb, cb_opaque);
|
|
|
|
}
|
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
BlockAIOCB *dma_blk_read(BlockBackend *blk,
|
2016-10-27 22:29:13 +02:00
|
|
|
QEMUSGList *sg, uint64_t offset, uint32_t align,
|
2014-10-07 13:59:18 +02:00
|
|
|
void (*cb)(void *opaque, int ret), void *opaque)
|
2009-02-05 22:23:58 +01:00
|
|
|
{
|
2016-10-27 22:29:13 +02:00
|
|
|
return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
|
|
|
|
dma_blk_read_io_func, blk, cb, opaque,
|
2014-10-07 13:59:18 +02:00
|
|
|
DMA_DIRECTION_FROM_DEVICE);
|
2009-02-05 22:23:58 +01:00
|
|
|
}
|
|
|
|
|
2016-05-23 14:54:06 +02:00
|
|
|
static
|
|
|
|
BlockAIOCB *dma_blk_write_io_func(int64_t offset, QEMUIOVector *iov,
|
|
|
|
BlockCompletionFunc *cb, void *cb_opaque,
|
|
|
|
void *opaque)
|
|
|
|
{
|
|
|
|
BlockBackend *blk = opaque;
|
|
|
|
return blk_aio_pwritev(blk, offset, iov, 0, cb, cb_opaque);
|
|
|
|
}
|
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
BlockAIOCB *dma_blk_write(BlockBackend *blk,
|
2016-10-27 22:29:13 +02:00
|
|
|
QEMUSGList *sg, uint64_t offset, uint32_t align,
|
2014-10-07 13:59:18 +02:00
|
|
|
void (*cb)(void *opaque, int ret), void *opaque)
|
2009-02-05 22:23:58 +01:00
|
|
|
{
|
2016-10-27 22:29:13 +02:00
|
|
|
return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
|
|
|
|
dma_blk_write_io_func, blk, cb, opaque,
|
2014-10-07 13:59:18 +02:00
|
|
|
DMA_DIRECTION_TO_DEVICE);
|
2009-02-05 22:23:58 +01:00
|
|
|
}
|
2011-07-06 08:02:14 +02:00
|
|
|
|
|
|
|
|
2012-06-27 06:50:40 +02:00
|
|
|
static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
|
|
|
|
DMADirection dir)
|
2011-07-06 08:02:14 +02:00
|
|
|
{
|
|
|
|
uint64_t resid;
|
|
|
|
int sg_cur_index;
|
|
|
|
|
|
|
|
resid = sg->size;
|
|
|
|
sg_cur_index = 0;
|
|
|
|
len = MIN(len, resid);
|
|
|
|
while (len > 0) {
|
|
|
|
ScatterGatherEntry entry = sg->sg[sg_cur_index++];
|
|
|
|
int32_t xfer = MIN(len, entry.len);
|
2013-04-10 18:15:49 +02:00
|
|
|
dma_memory_rw(sg->as, entry.base, ptr, xfer, dir);
|
2011-07-06 08:02:14 +02:00
|
|
|
ptr += xfer;
|
|
|
|
len -= xfer;
|
|
|
|
resid -= xfer;
|
|
|
|
}
|
|
|
|
|
|
|
|
return resid;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
|
|
|
|
{
|
2012-06-27 06:50:40 +02:00
|
|
|
return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
|
2011-07-06 08:02:14 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
|
|
|
|
{
|
2012-06-27 06:50:40 +02:00
|
|
|
return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
|
2011-07-06 08:02:14 +02:00
|
|
|
}
|
2011-09-05 14:20:29 +02:00
|
|
|
|
2014-10-07 13:59:18 +02:00
|
|
|
void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
|
2011-09-05 14:20:29 +02:00
|
|
|
QEMUSGList *sg, enum BlockAcctType type)
|
|
|
|
{
|
2014-10-07 13:59:18 +02:00
|
|
|
block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
|
2011-09-05 14:20:29 +02:00
|
|
|
}
|