2014-05-08 10:58:44 +02:00
|
|
|
#ifndef HW_USB_UHCI_REGS_H
|
2016-06-29 15:29:06 +02:00
|
|
|
#define HW_USB_UHCI_REGS_H
|
2014-05-08 10:58:44 +02:00
|
|
|
|
|
|
|
#define UHCI_CMD_FGR (1 << 4)
|
|
|
|
#define UHCI_CMD_EGSM (1 << 3)
|
|
|
|
#define UHCI_CMD_GRESET (1 << 2)
|
|
|
|
#define UHCI_CMD_HCRESET (1 << 1)
|
|
|
|
#define UHCI_CMD_RS (1 << 0)
|
|
|
|
|
|
|
|
#define UHCI_STS_HCHALTED (1 << 5)
|
|
|
|
#define UHCI_STS_HCPERR (1 << 4)
|
|
|
|
#define UHCI_STS_HSERR (1 << 3)
|
|
|
|
#define UHCI_STS_RD (1 << 2)
|
|
|
|
#define UHCI_STS_USBERR (1 << 1)
|
|
|
|
#define UHCI_STS_USBINT (1 << 0)
|
|
|
|
|
|
|
|
#define TD_CTRL_SPD (1 << 29)
|
|
|
|
#define TD_CTRL_ERROR_SHIFT 27
|
|
|
|
#define TD_CTRL_IOS (1 << 25)
|
|
|
|
#define TD_CTRL_IOC (1 << 24)
|
|
|
|
#define TD_CTRL_ACTIVE (1 << 23)
|
|
|
|
#define TD_CTRL_STALL (1 << 22)
|
|
|
|
#define TD_CTRL_BABBLE (1 << 20)
|
|
|
|
#define TD_CTRL_NAK (1 << 19)
|
|
|
|
#define TD_CTRL_TIMEOUT (1 << 18)
|
|
|
|
|
|
|
|
#define UHCI_PORT_SUSPEND (1 << 12)
|
|
|
|
#define UHCI_PORT_RESET (1 << 9)
|
|
|
|
#define UHCI_PORT_LSDA (1 << 8)
|
2014-05-08 11:42:53 +02:00
|
|
|
#define UHCI_PORT_RSVD1 (1 << 7)
|
2014-05-08 10:58:44 +02:00
|
|
|
#define UHCI_PORT_RD (1 << 6)
|
|
|
|
#define UHCI_PORT_ENC (1 << 3)
|
|
|
|
#define UHCI_PORT_EN (1 << 2)
|
|
|
|
#define UHCI_PORT_CSC (1 << 1)
|
|
|
|
#define UHCI_PORT_CCS (1 << 0)
|
|
|
|
|
|
|
|
#define UHCI_PORT_READ_ONLY (0x1bb)
|
|
|
|
#define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
|
|
|
|
|
|
|
|
#endif /* HW_USB_UHCI_REGS_H */
|