2023-10-01 23:56:04 +02:00
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# SPDX-License-Identifier: LGPL-2.0+
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#
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# Sparc instruction decode definitions.
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# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
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2023-10-02 01:48:18 +02:00
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##
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## Major Opcodes 00 and 01 -- branches, call, and sethi.
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##
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2023-10-02 00:57:34 +02:00
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&bcc i a cond cc
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BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
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Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
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2023-10-04 22:00:53 +02:00
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FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
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FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
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2023-10-02 00:57:34 +02:00
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2023-10-02 01:23:14 +02:00
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%d16 20:s2 0:14
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BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
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2023-10-04 22:00:53 +02:00
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NCP 00 - ---- 111 ---------------------- # CBcc
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2023-10-02 01:48:18 +02:00
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SETHI 00 rd:5 100 i:22
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2023-10-02 00:11:00 +02:00
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CALL 01 i:s30
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2023-10-02 03:29:42 +02:00
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2023-10-02 09:25:46 +02:00
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##
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## Major Opcode 10 -- integer, floating-point, vis, and system insns.
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##
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&r_r_ri rd rs1 rs2_or_imm imm:bool
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@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
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2023-10-05 02:51:37 +02:00
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@r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri
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2023-10-02 09:25:46 +02:00
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2023-10-02 06:49:43 +02:00
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&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
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@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
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2023-10-02 07:46:24 +02:00
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@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
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2023-10-02 23:40:04 +02:00
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@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
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2023-10-02 06:49:43 +02:00
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2023-10-02 04:21:38 +02:00
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{
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[
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STBAR 10 00000 101000 01111 0 0000000000000
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MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
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RDCCR 10 rd:5 101000 00010 0 0000000000000
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RDASI 10 rd:5 101000 00011 0 0000000000000
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RDTICK 10 rd:5 101000 00100 0 0000000000000
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RDPC 10 rd:5 101000 00101 0 0000000000000
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RDFPRS 10 rd:5 101000 00110 0 0000000000000
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RDASR17 10 rd:5 101000 10001 0 0000000000000
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RDGSR 10 rd:5 101000 10011 0 0000000000000
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RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
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RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
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RDSTICK 10 rd:5 101000 11000 0 0000000000000
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RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000
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RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000
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]
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# Before v8, all rs1 accepted; otherwise rs1==0.
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RDY 10 rd:5 101000 rs1:5 0 0000000000000
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}
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2023-10-02 09:25:46 +02:00
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{
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[
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WRY 10 00000 110000 ..... . ............. @n_r_ri
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WRCCR 10 00010 110000 ..... . ............. @n_r_ri
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WRASI 10 00011 110000 ..... . ............. @n_r_ri
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WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
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{
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WRGSR 10 10011 110000 ..... . ............. @n_r_ri
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WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
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}
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WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri
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WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri
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WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri
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WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri
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WRSTICK 10 11000 110000 ..... . ............. @n_r_ri
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WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri
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]
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# Before v8, rs1==0 was WRY, and the rest executed as nop.
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[
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NOP_v7 10 ----- 110000 ----- 0 00000000 -----
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NOP_v7 10 ----- 110000 ----- 1 -------- -----
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]
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}
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2023-10-02 05:34:14 +02:00
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{
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RDPSR 10 rd:5 101001 00000 0 0000000000000
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RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000
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}
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RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000
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RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000
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RDHPR_htba 10 rd:5 101001 00101 0 0000000000000
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RDHPR_hver 10 rd:5 101001 00110 0 0000000000000
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RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000
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2023-10-02 16:38:42 +02:00
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{
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WRPSR 10 00000 110001 ..... . ............. @n_r_ri
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SAVED 10 00000 110001 00000 0 0000000000000
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}
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RESTORED 10 00001 110001 00000 0 0000000000000
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# UA2005 ALLCLEAN
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# UA2005 OTHERW
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# UA2005 NORMALW
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# UA2005 INVALW
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2023-10-02 06:21:43 +02:00
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{
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RDWIM 10 rd:5 101010 00000 0 0000000000000
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RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
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}
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RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000
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RDPR_tstate 10 rd:5 101010 00010 0 0000000000000
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RDPR_tt 10 rd:5 101010 00011 0 0000000000000
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RDPR_tick 10 rd:5 101010 00100 0 0000000000000
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RDPR_tba 10 rd:5 101010 00101 0 0000000000000
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RDPR_pstate 10 rd:5 101010 00110 0 0000000000000
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RDPR_tl 10 rd:5 101010 00111 0 0000000000000
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RDPR_pil 10 rd:5 101010 01000 0 0000000000000
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RDPR_cwp 10 rd:5 101010 01001 0 0000000000000
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RDPR_cansave 10 rd:5 101010 01010 0 0000000000000
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RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000
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RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000
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RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000
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RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
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RDPR_gl 10 rd:5 101010 10000 0 0000000000000
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RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
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RDPR_ver 10 rd:5 101010 11111 0 0000000000000
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2023-10-02 22:31:20 +02:00
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{
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WRWIM 10 00000 110010 ..... . ............. @n_r_ri
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WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri
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}
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WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri
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WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri
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WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri
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WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri
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WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri
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WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri
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WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri
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WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri
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WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri
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WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri
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WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri
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WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri
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WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri
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WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri
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WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri
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WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri
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2023-10-02 06:29:10 +02:00
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{
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FLUSHW 10 00000 101011 00000 0 0000000000000
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RDTBR 10 rd:5 101011 00000 0 0000000000000
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}
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2023-10-02 22:46:42 +02:00
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{
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WRTBR 10 00000 110011 ..... . ............. @n_r_ri
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WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri
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}
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WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri
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WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
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WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
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WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
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2023-10-02 06:49:43 +02:00
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ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc
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AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc
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OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc
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XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc
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SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc
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ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc
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ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc
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XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
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2023-10-21 04:20:44 +02:00
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ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc
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2023-10-02 08:11:50 +02:00
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SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc
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2023-10-02 06:49:43 +02:00
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2023-10-02 07:46:24 +02:00
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MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
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2023-10-02 07:55:04 +02:00
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UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
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SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
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2023-10-02 23:40:04 +02:00
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MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1
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2023-10-02 07:46:24 +02:00
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2023-10-02 08:34:14 +02:00
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UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
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SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
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2023-10-02 08:46:47 +02:00
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UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
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SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
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2023-10-02 08:34:14 +02:00
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2023-10-02 23:40:04 +02:00
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TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1
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TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1
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TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1
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TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1
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2023-10-21 06:28:43 +02:00
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POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 \
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&r_r_ri_cc rs1=0 cc=0
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2023-10-02 23:48:10 +02:00
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&shiftr rd rs1 rs2 x:bool
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@shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr
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SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr
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SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr
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SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr
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&shifti rd rs1 i x:bool
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@shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti
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SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti
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SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti
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SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti
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2023-10-02 03:29:42 +02:00
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Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
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{
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# For v7, the entire simm13 field is present, but masked to 7 bits.
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# For v8, [12:7] are reserved. However, a compatibility note for
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# the Tcc insn in the v9 manual suggests that the v8 reserved field
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# was ignored and did not produce traps.
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Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
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# For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
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# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
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Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
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}
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2023-10-05 00:37:54 +02:00
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MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11
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MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11
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MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10
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2023-10-04 21:43:44 +02:00
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2023-10-05 02:51:37 +02:00
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JMPL 10 ..... 111000 ..... . ............. @r_r_ri
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{
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RETT 10 00000 111001 ..... . ............. @n_r_ri
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RETURN 10 00000 111001 ..... . ............. @n_r_ri
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}
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2023-10-05 03:52:38 +02:00
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NOP 10 00000 111011 ----- 0 00000000----- # FLUSH reg+reg
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NOP 10 00000 111011 ----- 1 ------------- # FLUSH reg+imm
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SAVE 10 ..... 111100 ..... . ............. @r_r_ri
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RESTORE 10 ..... 111101 ..... . ............. @r_r_ri
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2023-10-05 02:51:37 +02:00
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2023-10-05 04:05:45 +02:00
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DONE 10 00000 111110 00000 0 0000000000000
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RETRY 10 00001 111110 00000 0 0000000000000
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2023-10-05 09:20:37 +02:00
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NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
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NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
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target/sparc: Move simple integer load/store to decodetree
Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX,
STW, STB, STH, STD, STX.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-05 04:50:47 +02:00
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##
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## Major Opcode 11 -- load and store instructions
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##
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2023-10-05 10:38:50 +02:00
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%dfp_rd 25:5 !function=extract_dfpreg
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%qfp_rd 25:5 !function=extract_qfpreg
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target/sparc: Move simple integer load/store to decodetree
Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX,
STW, STB, STH, STD, STX.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-05 04:50:47 +02:00
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&r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool
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@r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1
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2023-10-05 10:38:50 +02:00
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@d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \
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&r_r_ri_asi rd=%dfp_rd asi=-1
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@q_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \
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&r_r_ri_asi rd=%qfp_rd asi=-1
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target/sparc: Move asi integer load/store to decodetree
Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA,
STBA, STDA, STHA, STWA, STXA.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-05 08:19:55 +02:00
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@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0
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@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \
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&r_r_ri_asi imm=1 asi=-2
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2023-10-05 10:56:02 +02:00
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@d_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \
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&r_r_ri_asi rd=%dfp_rd imm=0
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@d_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \
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&r_r_ri_asi rd=%dfp_rd imm=1 asi=-2
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@q_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \
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&r_r_ri_asi rd=%qfp_rd imm=0
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@q_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \
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&r_r_ri_asi rd=%qfp_rd imm=1 asi=-2
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2023-10-05 09:09:36 +02:00
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@casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \
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&r_r_ri_asi imm=1 asi=-2
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target/sparc: Move simple integer load/store to decodetree
Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX,
STW, STB, STH, STD, STX.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-05 04:50:47 +02:00
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LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na
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LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na
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LDUH 11 ..... 000010 ..... . ............. @r_r_ri_na
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LDD 11 ..... 000011 ..... . ............. @r_r_ri_na
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LDSW 11 ..... 001000 ..... . ............. @r_r_ri_na
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LDSB 11 ..... 001001 ..... . ............. @r_r_ri_na
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LDSH 11 ..... 001010 ..... . ............. @r_r_ri_na
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LDX 11 ..... 001011 ..... . ............. @r_r_ri_na
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STW 11 ..... 000100 ..... . ............. @r_r_ri_na
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STB 11 ..... 000101 ..... . ............. @r_r_ri_na
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STH 11 ..... 000110 ..... . ............. @r_r_ri_na
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STD 11 ..... 000111 ..... . ............. @r_r_ri_na
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STX 11 ..... 001110 ..... . ............. @r_r_ri_na
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target/sparc: Move asi integer load/store to decodetree
Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA,
STBA, STDA, STHA, STWA, STXA.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-05 08:19:55 +02:00
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LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LDUWA
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LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LDUWA
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LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LDUBA
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LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LDUBA
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LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LDUHA
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LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LDUHA
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LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LDDA
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LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LDDA
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LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LDXA
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LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LDXA
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LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LDSBA
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LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LDSBA
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LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LDSHA
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LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LDSHA
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LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LDSWA
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LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LDSWA
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STW 11 ..... 010100 ..... . ............. @r_r_r_asi # STWA
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STW 11 ..... 010100 ..... . ............. @r_r_i_asi # STWA
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STB 11 ..... 010101 ..... . ............. @r_r_r_asi # STBA
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STB 11 ..... 010101 ..... . ............. @r_r_i_asi # STBA
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STH 11 ..... 010110 ..... . ............. @r_r_r_asi # STHA
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STH 11 ..... 010110 ..... . ............. @r_r_i_asi # STHA
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STD 11 ..... 010111 ..... . ............. @r_r_r_asi # STDA
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STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA
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STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA
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STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA
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2023-10-05 10:38:50 +02:00
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LDF 11 ..... 100000 ..... . ............. @r_r_ri_na
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2023-10-05 11:12:59 +02:00
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LDFSR 11 00000 100001 ..... . ............. @n_r_ri
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LDXFSR 11 00001 100001 ..... . ............. @n_r_ri
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2023-10-05 10:38:50 +02:00
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LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na
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LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na
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STF 11 ..... 100100 ..... . ............. @r_r_ri_na
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2023-10-05 11:12:59 +02:00
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STFSR 11 00000 100101 ..... . ............. @n_r_ri
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STXFSR 11 00001 100101 ..... . ............. @n_r_ri
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2023-10-05 10:38:50 +02:00
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{
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STQF 11 ..... 100110 ..... . ............. @q_r_ri_na
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STDFQ 11 ----- 100110 ----- - -------------
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}
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STDF 11 ..... 100111 ..... . ............. @d_r_ri_na
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2023-10-05 08:29:37 +02:00
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LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na
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LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA
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LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA
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2023-10-05 08:45:21 +02:00
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SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na
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SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA
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SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA
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2023-10-05 09:09:36 +02:00
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CASA 11 ..... 111100 ..... . ............. @r_r_r_asi
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CASA 11 ..... 111100 ..... . ............. @casa_imm
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CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi
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CASXA 11 ..... 111110 ..... . ............. @casa_imm
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2023-10-05 09:20:37 +02:00
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NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH
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NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH
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NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA
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2023-10-04 21:43:44 +02:00
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2023-10-05 10:56:02 +02:00
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{
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[
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LDFA 11 ..... 110000 ..... . ............. @r_r_r_asi
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LDFA 11 ..... 110000 ..... . ............. @r_r_i_asi
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]
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NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
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}
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2023-10-04 21:43:44 +02:00
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NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR
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2023-10-05 10:56:02 +02:00
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LDQFA 11 ..... 110010 ..... . ............. @q_r_r_asi
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LDQFA 11 ..... 110010 ..... . ............. @q_r_i_asi
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{
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[
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LDDFA 11 ..... 110011 ..... . ............. @d_r_r_asi
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LDDFA 11 ..... 110011 ..... . ............. @d_r_i_asi
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]
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NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC
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}
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{
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[
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STFA 11 ..... 110100 ..... . ............. @r_r_r_asi
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STFA 11 ..... 110100 ..... . ............. @r_r_i_asi
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]
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NCP 11 ----- 110100 ----- --------- ----- # v8 STC
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}
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2023-10-04 21:43:44 +02:00
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NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR
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2023-10-05 10:56:02 +02:00
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{
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[
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STQFA 11 ..... 110110 ..... . ............. @q_r_r_asi
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STQFA 11 ..... 110110 ..... . ............. @q_r_i_asi
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]
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NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ
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}
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{
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[
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STDFA 11 ..... 110111 ..... . ............. @d_r_r_asi
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STDFA 11 ..... 110111 ..... . ............. @d_r_i_asi
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]
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NCP 11 ----- 110111 ----- --------- ----- # v8 STDC
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}
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