155 lines
3.7 KiB
ArmAsm
155 lines
3.7 KiB
ArmAsm
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/*
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* Test ARMv6-M UNDEFINED 32-bit instructions
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*
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* Copyright 2018 Red Hat Inc.
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*
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* This work is licensed under the terms of the GNU GPL, version 2
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* or later. See the COPYING file in the top-level directory.
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*/
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/*
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* Test that UNDEFINED 32-bit instructions fault as expected. This is an
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* interesting test because ARMv6-M shares code with its more fully-featured
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* siblings and it's necessary to verify that its limited instruction set is
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* emulated correctly.
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*
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* The emulator must be invoked with -semihosting so that the test case can
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* terminate with exit code 0 on success or 1 on failure.
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*
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* Failures can be debugged with -d in_asm,int,exec,cpu and the
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* gdbstub (-S -s).
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*/
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.syntax unified
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.cpu cortex-m0
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.thumb
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/*
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* Memory map
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*/
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#define SRAM_BASE 0x20000000
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#define SRAM_SIZE (16 * 1024)
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/*
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* Semihosting interface on ARM T32
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* See "Semihosting for AArch32 and AArch64 Version 2.0 Documentation" by ARM
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*/
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#define semihosting_call bkpt 0xab
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#define SYS_EXIT 0x18
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vector_table:
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.word SRAM_BASE + SRAM_SIZE /* 0. SP_main */
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.word exc_reset_thumb /* 1. Reset */
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.word 0 /* 2. NMI */
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.word exc_hard_fault_thumb /* 3. HardFault */
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.rept 7
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.word 0 /* 4-10. Reserved */
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.endr
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.word 0 /* 11. SVCall */
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.word 0 /* 12. Reserved */
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.word 0 /* 13. Reserved */
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.word 0 /* 14. PendSV */
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.word 0 /* 15. SysTick */
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.rept 32
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.word 0 /* 16-47. External Interrupts */
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.endr
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exc_reset:
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.equ exc_reset_thumb, exc_reset + 1
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.global exc_reset_thumb
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/* The following 32-bit UNDEFINED instructions are tested by executing
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* them. The HardFault exception handler should execute and return to
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* the next test case. If no exception is raised the test fails.
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*/
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/* Table A5-9 32-bit Thumb encoding */
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.short 0b1110100000000000
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.short 0b0000000000000000
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b not_reached
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.short 0b1110100000000000
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.short 0b1000000000000000
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b not_reached
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.short 0b1111100000000000
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.short 0b0000000000000000
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b not_reached
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.short 0b1111100000000000
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.short 0b1000000000000000
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b not_reached
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.short 0b1111000000000000
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.short 0b0000000000000000
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b not_reached
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/* Table A5-10 Branch and miscellaneous control instructions */
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.short 0b1111011111110000
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.short 0b1010000000000000
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b not_reached
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/* The following are valid 32-bit instructions that must not raise a
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* HardFault.
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*/
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/* B4.2.3 Move to Special Register (moves to IPSR are ignored) */
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msr ipsr, r0
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b 1f
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b not_reached
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1:
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/* B4.2.2 Move from Special Register */
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mrs r0, ipsr
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b 1f
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b not_reached
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1:
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/* A6.7.13 Branch with Link (immediate) */
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bl 1f
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1:
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b 1f
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b not_reached
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1:
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/* A6.7.21 Data Memory Barrier */
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dmb
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b 1f
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b not_reached
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1:
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/* A6.7.22 Data Synchronization Barrier */
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dsb
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b 1f
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b not_reached
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1:
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/* A6.7.24 Instruction Memory Barrier */
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isb
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b 1f
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b not_reached
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1:
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/* Success! */
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movs r0, 1
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b exit
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not_reached: /* Failure :( */
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movs r0, 0
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b exit
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/* When a HardFault occurs, return to pc+6 (test cases are 3 halfwords long) */
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exc_hard_fault:
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.equ exc_hard_fault_thumb, exc_hard_fault + 1
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.global exc_hard_fault_thumb
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ldr r0, [sp, 0x18]
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adds r0, 6
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str r0, [sp, 0x18]
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bx lr
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/*
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* exit: Terminate emulator
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* @r0: 0 - failure, 1 - success
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*/
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exit:
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movs r1, 0
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cmp r0, 1
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bne 1f
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ldr r1, ADP_Stopped_ApplicationExit
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1:
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movs r0, SYS_EXIT
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semihosting_call
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.align 2
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ADP_Stopped_ApplicationExit:
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.word 0x20026
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