357 lines
10 KiB
C
357 lines
10 KiB
C
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/*
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* S390x MMU related functions
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*
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* Copyright (c) 2011 Alexander Graf
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* Copyright (c) 2015 Thomas Huth, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "cpu.h"
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/* #define DEBUG_S390 */
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/* #define DEBUG_S390_PTE */
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/* #define DEBUG_S390_STDOUT */
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#ifdef DEBUG_S390
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#ifdef DEBUG_S390_STDOUT
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); \
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qemu_log(fmt, ##__VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
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#endif
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#ifdef DEBUG_S390_PTE
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#define PTE_DPRINTF DPRINTF
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#else
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#define PTE_DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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static int trans_bits(CPUS390XState *env, uint64_t mode)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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int bits = 0;
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switch (mode) {
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case PSW_ASC_PRIMARY:
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bits = 1;
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break;
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case PSW_ASC_SECONDARY:
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bits = 2;
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break;
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case PSW_ASC_HOME:
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bits = 3;
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break;
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default:
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cpu_abort(CPU(cpu), "unknown asc mode\n");
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break;
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}
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return bits;
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}
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static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
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uint64_t mode)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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int ilen = ILEN_LATER_INC;
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int bits = trans_bits(env, mode) | 4;
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DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
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stq_phys(cs->as,
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env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
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trigger_pgm_exception(env, PGM_PROTECTION, ilen);
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}
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static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
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uint32_t type, uint64_t asc, int rw)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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int ilen = ILEN_LATER;
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int bits = trans_bits(env, asc);
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/* Code accesses have an undefined ilc. */
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if (rw == 2) {
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ilen = 2;
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}
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DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
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stq_phys(cs->as,
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env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
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trigger_pgm_exception(env, type, ilen);
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}
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/**
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* Translate real address to absolute (= physical)
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* address by taking care of the prefix mapping.
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*/
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static target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
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{
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if (raddr < 0x2000) {
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return raddr + env->psa; /* Map the lowcore. */
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} else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
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return raddr - env->psa; /* Map the 0 page. */
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}
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return raddr;
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}
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/* Decode page table entry (normal 4KB page) */
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static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t asce,
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target_ulong *raddr, int *flags, int rw)
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{
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if (asce & _PAGE_INVALID) {
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DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, asce);
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trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
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return -1;
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}
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if (asce & _PAGE_RO) {
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*flags &= ~PAGE_WRITE;
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}
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*raddr = asce & _ASCE_ORIGIN;
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PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, asce);
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return 0;
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}
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/* Decode EDAT1 segment frame absolute address (1MB page) */
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static int mmu_translate_sfaa(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t asce, target_ulong *raddr,
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int *flags, int rw)
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{
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if (asce & _SEGMENT_ENTRY_INV) {
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DPRINTF("%s: SEG=0x%" PRIx64 " invalid\n", __func__, asce);
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trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
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return -1;
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}
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if (asce & _SEGMENT_ENTRY_RO) {
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*flags &= ~PAGE_WRITE;
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}
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*raddr = (asce & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
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PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, asce);
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return 0;
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}
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static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t asce, int level,
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target_ulong *raddr, int *flags, int rw)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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uint64_t offs = 0;
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uint64_t origin;
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uint64_t new_asce;
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PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
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if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
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((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
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/* XXX different regions have different faults */
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DPRINTF("%s: invalid region\n", __func__);
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trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
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return -1;
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}
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if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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if (asce & _ASCE_REAL_SPACE) {
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/* direct mapping */
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*raddr = vaddr;
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return 0;
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}
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origin = asce & _ASCE_ORIGIN;
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switch (level) {
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case _ASCE_TYPE_REGION1 + 4:
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offs = (vaddr >> 50) & 0x3ff8;
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break;
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case _ASCE_TYPE_REGION1:
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offs = (vaddr >> 39) & 0x3ff8;
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break;
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case _ASCE_TYPE_REGION2:
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offs = (vaddr >> 28) & 0x3ff8;
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break;
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case _ASCE_TYPE_REGION3:
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offs = (vaddr >> 17) & 0x3ff8;
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break;
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case _ASCE_TYPE_SEGMENT:
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offs = (vaddr >> 9) & 0x07f8;
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origin = asce & _SEGMENT_ENTRY_ORIGIN;
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break;
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}
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/* XXX region protection flags */
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/* *flags &= ~PAGE_WRITE */
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new_asce = ldq_phys(cs->as, origin + offs);
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PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
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__func__, origin, offs, new_asce);
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if (level == _ASCE_TYPE_SEGMENT) {
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/* 4KB page */
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return mmu_translate_pte(env, vaddr, asc, new_asce, raddr, flags, rw);
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} else if (level - 4 == _ASCE_TYPE_SEGMENT &&
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(new_asce & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
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/* 1MB page */
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return mmu_translate_sfaa(env, vaddr, asc, new_asce, raddr, flags, rw);
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} else {
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/* yet another region */
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return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
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flags, rw);
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}
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}
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static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, target_ulong *raddr, int *flags,
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int rw)
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{
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uint64_t asce = 0;
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int level, new_level;
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int r;
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switch (asc) {
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case PSW_ASC_PRIMARY:
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PTE_DPRINTF("%s: asc=primary\n", __func__);
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asce = env->cregs[1];
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break;
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case PSW_ASC_SECONDARY:
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PTE_DPRINTF("%s: asc=secondary\n", __func__);
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asce = env->cregs[7];
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break;
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case PSW_ASC_HOME:
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PTE_DPRINTF("%s: asc=home\n", __func__);
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asce = env->cregs[13];
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break;
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}
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switch (asce & _ASCE_TYPE_MASK) {
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case _ASCE_TYPE_REGION1:
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break;
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case _ASCE_TYPE_REGION2:
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if (vaddr & 0xffe0000000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffe0000000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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break;
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case _ASCE_TYPE_REGION3:
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if (vaddr & 0xfffffc0000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xfffffc0000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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break;
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case _ASCE_TYPE_SEGMENT:
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if (vaddr & 0xffffffff80000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffffffff80000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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break;
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}
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/* fake level above current */
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level = asce & _ASCE_TYPE_MASK;
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new_level = level + 4;
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asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
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r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
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if ((rw == 1) && !(*flags & PAGE_WRITE)) {
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trigger_prot_fault(env, vaddr, asc);
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return -1;
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}
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return r;
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}
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags)
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{
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int r = -1;
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uint8_t *sk;
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*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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vaddr &= TARGET_PAGE_MASK;
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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*raddr = vaddr;
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r = 0;
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goto out;
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}
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switch (asc) {
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case PSW_ASC_PRIMARY:
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case PSW_ASC_HOME:
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r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
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break;
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case PSW_ASC_SECONDARY:
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/*
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* Instruction: Primary
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* Data: Secondary
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*/
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if (rw == 2) {
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r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
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rw);
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*flags &= ~(PAGE_READ | PAGE_WRITE);
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} else {
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r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
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rw);
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*flags &= ~(PAGE_EXEC);
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}
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break;
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case PSW_ASC_ACCREG:
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default:
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hw_error("guest switched to unknown asc mode\n");
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break;
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}
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out:
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/* Convert real address -> absolute address */
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*raddr = mmu_real2abs(env, *raddr);
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if (*raddr <= ram_size) {
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sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
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if (*flags & PAGE_READ) {
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*sk |= SK_R;
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}
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if (*flags & PAGE_WRITE) {
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*sk |= SK_C;
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}
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}
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return r;
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}
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