404 lines
8.9 KiB
C
404 lines
8.9 KiB
C
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/*
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* TriCore emulation for qemu: main CPU struct.
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*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined(__TRICORE_CPU_H__)
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#define __TRICORE_CPU_H__
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#include "tricore-defs.h"
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#include "config.h"
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#include "qemu-common.h"
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat.h"
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#define ELF_MACHINE EM_TRICORE
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#define CPUArchState struct CPUTriCoreState
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struct CPUTriCoreState;
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struct tricore_boot_info;
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#define NB_MMU_MODES 3
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typedef struct tricore_def_t tricore_def_t;
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typedef struct CPUTriCoreState CPUTriCoreState;
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struct CPUTriCoreState {
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/* GPR Register */
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uint32_t gpr_a[16];
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uint32_t gpr_d[16];
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/* CSFR Register */
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uint32_t PCXI;
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/* Frequently accessed PSW_USB bits are stored separately for efficiency.
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This contains all the other bits. Use psw_{read,write} to access
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the whole PSW. */
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uint32_t PSW;
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/* PSW flag cache for faster execution
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*/
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uint32_t PSW_USB_C;
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uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
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uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
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uint32_t PC;
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uint32_t SYSCON;
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uint32_t CPU_ID;
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uint32_t BIV;
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uint32_t BTV;
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uint32_t ISP;
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uint32_t ICR;
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uint32_t FCX;
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uint32_t LCX;
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uint32_t COMPAT;
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/* Mem Protection Register */
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uint32_t DPR0_0L;
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uint32_t DPR0_0U;
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uint32_t DPR0_1L;
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uint32_t DPR0_1U;
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uint32_t DPR0_2L;
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uint32_t DPR0_2U;
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uint32_t DPR0_3L;
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uint32_t DPR0_3U;
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uint32_t DPR1_0L;
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uint32_t DPR1_0U;
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uint32_t DPR1_1L;
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uint32_t DPR1_1U;
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uint32_t DPR1_2L;
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uint32_t DPR1_2U;
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uint32_t DPR1_3L;
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uint32_t DPR1_3U;
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uint32_t DPR2_0L;
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uint32_t DPR2_0U;
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uint32_t DPR2_1L;
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uint32_t DPR2_1U;
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uint32_t DPR2_2L;
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uint32_t DPR2_2U;
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uint32_t DPR2_3L;
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uint32_t DPR2_3U;
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uint32_t DPR3_0L;
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uint32_t DPR3_0U;
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uint32_t DPR3_1L;
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uint32_t DPR3_1U;
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uint32_t DPR3_2L;
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uint32_t DPR3_2U;
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uint32_t DPR3_3L;
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uint32_t DPR3_3U;
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uint32_t CPR0_0L;
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uint32_t CPR0_0U;
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uint32_t CPR0_1L;
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uint32_t CPR0_1U;
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uint32_t CPR0_2L;
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uint32_t CPR0_2U;
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uint32_t CPR0_3L;
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uint32_t CPR0_3U;
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uint32_t CPR1_0L;
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uint32_t CPR1_0U;
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uint32_t CPR1_1L;
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uint32_t CPR1_1U;
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uint32_t CPR1_2L;
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uint32_t CPR1_2U;
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uint32_t CPR1_3L;
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uint32_t CPR1_3U;
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uint32_t CPR2_0L;
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uint32_t CPR2_0U;
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uint32_t CPR2_1L;
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uint32_t CPR2_1U;
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uint32_t CPR2_2L;
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uint32_t CPR2_2U;
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uint32_t CPR2_3L;
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uint32_t CPR2_3U;
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uint32_t CPR3_0L;
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uint32_t CPR3_0U;
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uint32_t CPR3_1L;
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uint32_t CPR3_1U;
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uint32_t CPR3_2L;
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uint32_t CPR3_2U;
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uint32_t CPR3_3L;
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uint32_t CPR3_3U;
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uint32_t DPM0;
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uint32_t DPM1;
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uint32_t DPM2;
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uint32_t DPM3;
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uint32_t CPM0;
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uint32_t CPM1;
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uint32_t CPM2;
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uint32_t CPM3;
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/* Memory Management Registers */
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uint32_t MMU_CON;
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uint32_t MMU_ASI;
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uint32_t MMU_TVA;
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uint32_t MMU_TPA;
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uint32_t MMU_TPX;
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uint32_t MMU_TFA;
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/* {1.3.1 only */
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uint32_t BMACON;
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uint32_t SMACON;
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uint32_t DIEAR;
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uint32_t DIETR;
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uint32_t CCDIER;
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uint32_t MIECON;
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uint32_t PIEAR;
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uint32_t PIETR;
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uint32_t CCPIER;
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/*} */
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/* Debug Registers */
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uint32_t DBGSR;
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uint32_t EXEVT;
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uint32_t CREVT;
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uint32_t SWEVT;
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uint32_t TR0EVT;
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uint32_t TR1EVT;
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uint32_t DMS;
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uint32_t DCX;
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uint32_t DBGTCR;
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uint32_t CCTRL;
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uint32_t CCNT;
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uint32_t ICNT;
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uint32_t M1CNT;
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uint32_t M2CNT;
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uint32_t M3CNT;
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/* Floating Point Registers */
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/* XXX: */
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/* QEMU */
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int error_code;
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uint32_t hflags; /* CPU State */
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CPU_COMMON
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/* Internal CPU feature flags. */
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uint64_t features;
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const tricore_def_t *cpu_model;
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void *irq[8];
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struct QEMUTimer *timer; /* Internal timer */
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};
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#define MASK_PCXI_PCPN 0xff000000
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#define MASK_PCXI_PIE 0x00800000
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#define MASK_PCXI_UL 0x00400000
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#define MASK_PCXI_PCXS 0x000f0000
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#define MASK_PCXI_PCXO 0x0000ffff
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#define MASK_PSW_USB 0xff000000
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#define MASK_USB_C 0x80000000
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#define MASK_USB_V 0x40000000
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#define MASK_USB_SV 0x20000000
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#define MASK_USB_AV 0x10000000
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#define MASK_USB_SAV 0x08000000
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#define MASK_PSW_PRS 0x00003000
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#define MASK_PSW_IO 0x00000c00
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#define MASK_PSW_IS 0x00000200
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#define MASK_PSW_GW 0x00000100
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#define MASK_PSW_CDE 0x00000080
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#define MASK_PSW_CDC 0x0000007f
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#define MASK_SYSCON_PRO_TEN 0x2
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#define MASK_SYSCON_FCD_SF 0x1
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#define MASK_CPUID_MOD 0xffff0000
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#define MASK_CPUID_MOD_32B 0x0000ff00
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#define MASK_CPUID_REV 0x000000ff
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#define MASK_ICR_PIPN 0x00ff0000
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#define MASK_ICR_IE 0x00000100
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#define MASK_ICR_CCPN 0x000000ff
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#define MASK_FCX_FCXS 0x000f0000
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#define MASK_FCX_FCXO 0x0000ffff
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#define MASK_LCX_LCXS 0x000f0000
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#define MASK_LCX_LCX0 0x0000ffff
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#define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
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#define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
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#define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
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enum tricore_features {
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TRICORE_FEATURE_13,
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TRICORE_FEATURE_131,
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TRICORE_FEATURE_16,
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};
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static inline int tricore_feature(CPUTriCoreState *env, int feature)
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{
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return (env->features & (1ULL << feature)) != 0;
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}
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/* TriCore Traps Classes*/
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enum {
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TRAPC_NONE = -1,
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TRAPC_MMU = 0,
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TRAPC_PROT = 1,
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TRAPC_INSN_ERR = 2,
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TRAPC_CTX_MNG = 3,
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TRAPC_SYSBUS = 4,
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TRAPC_ASSERT = 5,
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TRAPC_SYSCALL = 6,
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TRAPC_NMI = 7,
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};
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/* Class 0 TIN */
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enum {
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TIN0_VAF = 0,
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TIN0_VAP = 1,
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};
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/* Class 1 TIN */
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enum {
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TIN1_PRIV = 1,
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TIN1_MPR = 2,
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TIN1_MPW = 3,
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TIN1_MPX = 4,
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TIN1_MPP = 5,
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TIN1_MPN = 6,
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TIN1_GRWP = 7,
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};
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/* Class 2 TIN */
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enum {
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TIN2_IOPC = 1,
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TIN2_UOPC = 2,
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TIN2_OPD = 3,
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TIN2_ALN = 4,
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TIN2_MEM = 5,
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};
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/* Class 3 TIN */
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enum {
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TIN3_FCD = 1,
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TIN3_CDO = 2,
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TIN3_CDU = 3,
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TIN3_FCU = 4,
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TIN3_CSU = 5,
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TIN3_CTYP = 6,
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TIN3_NEST = 7,
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};
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/* Class 4 TIN */
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enum {
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TIN4_PSE = 1,
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TIN4_DSE = 2,
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TIN4_DAE = 3,
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TIN4_CAE = 4,
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TIN4_PIE = 5,
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TIN4_DIE = 6,
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};
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/* Class 5 TIN */
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enum {
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TIN5_OVF = 1,
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TIN5_SOVF = 1,
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};
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/* Class 6 TIN
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*
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* Is always TIN6_SYS
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*/
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/* Class 7 TIN */
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enum {
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TIN7_NMI = 0,
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};
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uint32_t psw_read(CPUTriCoreState *env);
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void psw_write(CPUTriCoreState *env, uint32_t val);
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#include "cpu-qom.h"
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#define MMU_USER_IDX 2
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void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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#define cpu_exec cpu_tricore_exec
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#define cpu_signal_handler cpu_tricore_signal_handler
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#define cpu_list tricore_cpu_list
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static inline int cpu_mmu_index(CPUTriCoreState *env)
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{
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return 0;
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}
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#include "exec/cpu-all.h"
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enum {
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/* 1 bit to define user level / supervisor access */
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ACCESS_USER = 0x00,
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ACCESS_SUPER = 0x01,
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/* 1 bit to indicate direction */
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ACCESS_STORE = 0x02,
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/* Type of instruction that generated the access */
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ACCESS_CODE = 0x10, /* Code fetch access */
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ACCESS_INT = 0x20, /* Integer load/store access */
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ACCESS_FLOAT = 0x30, /* floating point load/store access */
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};
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void cpu_state_reset(CPUTriCoreState *s);
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int cpu_tricore_exec(CPUTriCoreState *s);
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void tricore_tcg_init(void);
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int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
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static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->PC;
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|
|
*cs_base = 0;
|
||
|
|
*flags = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
TriCoreCPU *cpu_tricore_init(const char *cpu_model);
|
||
|
|
|
||
|
|
static inline CPUTriCoreState *cpu_init(const char *cpu_model)
|
||
|
|
{
|
||
|
|
TriCoreCPU *cpu = cpu_tricore_init(cpu_model);
|
||
|
|
if (cpu == NULL) {
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
return &cpu->env;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* helpers.c */
|
||
|
|
int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,
|
||
|
|
int rw, int mmu_idx);
|
||
|
|
#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault
|
||
|
|
|
||
|
|
#include "exec/exec-all.h"
|
||
|
|
|
||
|
|
static inline void cpu_pc_from_tb(CPUTriCoreState *env, TranslationBlock *tb)
|
||
|
|
{
|
||
|
|
env->PC = tb->pc;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /*__TRICORE_CPU_H__ */
|