2019-10-26 18:45:42 +02:00
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/*
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* QEMU Macintosh Nubus
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*
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* Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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2021-09-24 09:37:49 +02:00
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/*
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* References:
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* Nubus Specification (TI)
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* http://www.bitsavers.org/pdf/ti/nubus/2242825-0001_NuBus_Spec1983.pdf
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*
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* Designing Cards and Drivers for the Macintosh Family (Apple)
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*/
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2019-10-26 18:45:42 +02:00
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#include "qemu/osdep.h"
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#include "hw/nubus/nubus.h"
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#include "qapi/error.h"
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2021-09-24 09:37:55 +02:00
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#include "trace.h"
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2019-10-26 18:45:42 +02:00
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static NubusBus *nubus_find(void)
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{
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/* Returns NULL unless there is exactly one nubus device */
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return NUBUS_BUS(object_resolve_path_type("", TYPE_NUBUS_BUS, NULL));
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}
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2021-09-24 09:37:56 +02:00
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static MemTxResult nubus_slot_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size, MemTxAttrs attrs)
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2019-10-26 18:45:42 +02:00
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{
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2021-09-24 09:37:55 +02:00
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trace_nubus_slot_write(addr, val, size);
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2021-09-24 09:37:56 +02:00
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return MEMTX_DECODE_ERROR;
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2019-10-26 18:45:42 +02:00
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}
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2021-09-24 09:37:56 +02:00
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static MemTxResult nubus_slot_read(void *opaque, hwaddr addr, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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2019-10-26 18:45:42 +02:00
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{
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2021-09-24 09:37:55 +02:00
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trace_nubus_slot_read(addr, size);
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2021-09-24 09:37:56 +02:00
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return MEMTX_DECODE_ERROR;
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2019-10-26 18:45:42 +02:00
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}
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static const MemoryRegionOps nubus_slot_ops = {
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2021-09-24 09:37:56 +02:00
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.read_with_attrs = nubus_slot_read,
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.write_with_attrs = nubus_slot_write,
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2019-10-26 18:45:42 +02:00
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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2021-09-24 09:37:55 +02:00
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.max_access_size = 4,
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2019-10-26 18:45:42 +02:00
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},
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};
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2021-09-24 09:37:56 +02:00
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static MemTxResult nubus_super_slot_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size,
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MemTxAttrs attrs)
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2019-10-26 18:45:42 +02:00
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{
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2021-09-24 09:37:55 +02:00
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trace_nubus_super_slot_write(addr, val, size);
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2021-09-24 09:37:56 +02:00
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return MEMTX_DECODE_ERROR;
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2019-10-26 18:45:42 +02:00
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}
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2021-09-24 09:37:56 +02:00
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static MemTxResult nubus_super_slot_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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2019-10-26 18:45:42 +02:00
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{
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2021-09-24 09:37:55 +02:00
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trace_nubus_super_slot_read(addr, size);
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2021-09-24 09:37:56 +02:00
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return MEMTX_DECODE_ERROR;
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2019-10-26 18:45:42 +02:00
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}
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static const MemoryRegionOps nubus_super_slot_ops = {
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2021-09-24 09:37:56 +02:00
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.read_with_attrs = nubus_super_slot_read,
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.write_with_attrs = nubus_super_slot_write,
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2019-10-26 18:45:42 +02:00
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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2021-09-24 09:37:55 +02:00
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.max_access_size = 4,
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2019-10-26 18:45:42 +02:00
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},
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};
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2021-09-24 09:38:00 +02:00
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static void nubus_unrealize(BusState *bus)
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{
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NubusBus *nubus = NUBUS_BUS(bus);
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address_space_destroy(&nubus->nubus_as);
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}
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2019-10-26 18:45:42 +02:00
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static void nubus_realize(BusState *bus, Error **errp)
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{
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2021-09-24 09:38:00 +02:00
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NubusBus *nubus = NUBUS_BUS(bus);
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2019-10-26 18:45:42 +02:00
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if (!nubus_find()) {
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error_setg(errp, "at most one %s device is permitted", TYPE_NUBUS_BUS);
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return;
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}
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2021-09-24 09:38:00 +02:00
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address_space_init(&nubus->nubus_as, &nubus->nubus_mr, "nubus");
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2019-10-26 18:45:42 +02:00
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}
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static void nubus_init(Object *obj)
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{
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NubusBus *nubus = NUBUS_BUS(obj);
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2021-09-24 09:38:00 +02:00
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memory_region_init(&nubus->nubus_mr, obj, "nubus", 0x100000000);
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2019-10-26 18:45:42 +02:00
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memory_region_init_io(&nubus->super_slot_io, obj, &nubus_super_slot_ops,
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nubus, "nubus-super-slots",
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2021-09-24 09:37:52 +02:00
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(NUBUS_SUPER_SLOT_NB + 1) * NUBUS_SUPER_SLOT_SIZE);
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2021-09-24 09:38:00 +02:00
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memory_region_add_subregion(&nubus->nubus_mr, 0x0, &nubus->super_slot_io);
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2019-10-26 18:45:42 +02:00
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memory_region_init_io(&nubus->slot_io, obj, &nubus_slot_ops,
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nubus, "nubus-slots",
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NUBUS_SLOT_NB * NUBUS_SLOT_SIZE);
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2021-09-24 09:38:00 +02:00
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memory_region_add_subregion(&nubus->nubus_mr,
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(NUBUS_SUPER_SLOT_NB + 1) *
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NUBUS_SUPER_SLOT_SIZE, &nubus->slot_io);
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2019-10-26 18:45:42 +02:00
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2021-09-24 09:37:52 +02:00
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nubus->slot_available_mask = MAKE_64BIT_MASK(NUBUS_FIRST_SLOT,
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NUBUS_SLOT_NB);
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2019-10-26 18:45:42 +02:00
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}
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2021-09-24 09:37:54 +02:00
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static char *nubus_get_dev_path(DeviceState *dev)
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{
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NubusDevice *nd = NUBUS_DEVICE(dev);
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BusState *bus = qdev_get_parent_bus(dev);
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char *p = qdev_get_dev_path(bus->parent);
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if (p) {
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char *ret = g_strdup_printf("%s/%s/%02x", p, bus->name, nd->slot);
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g_free(p);
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return ret;
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} else {
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return g_strdup_printf("%s/%02x", bus->name, nd->slot);
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}
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}
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2021-09-24 09:37:53 +02:00
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static bool nubus_check_address(BusState *bus, DeviceState *dev, Error **errp)
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{
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NubusDevice *nd = NUBUS_DEVICE(dev);
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NubusBus *nubus = NUBUS_BUS(bus);
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if (nd->slot == -1) {
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/* No slot specified, find first available free slot */
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int s = ctz32(nubus->slot_available_mask);
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if (s != 32) {
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nd->slot = s;
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} else {
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error_setg(errp, "Cannot register nubus card, no free slot "
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"available");
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return false;
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}
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} else {
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/* Slot specified, make sure the slot is available */
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if (!(nubus->slot_available_mask & BIT(nd->slot))) {
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error_setg(errp, "Cannot register nubus card, slot %d is "
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"unavailable or already occupied", nd->slot);
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return false;
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}
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}
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nubus->slot_available_mask &= ~BIT(nd->slot);
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return true;
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}
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2019-10-26 18:45:42 +02:00
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static void nubus_class_init(ObjectClass *oc, void *data)
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{
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BusClass *bc = BUS_CLASS(oc);
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bc->realize = nubus_realize;
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2021-09-24 09:38:00 +02:00
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bc->unrealize = nubus_unrealize;
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2021-09-24 09:37:53 +02:00
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bc->check_address = nubus_check_address;
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2021-09-24 09:37:54 +02:00
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bc->get_dev_path = nubus_get_dev_path;
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2019-10-26 18:45:42 +02:00
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}
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static const TypeInfo nubus_bus_info = {
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.name = TYPE_NUBUS_BUS,
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.parent = TYPE_BUS,
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.instance_size = sizeof(NubusBus),
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.instance_init = nubus_init,
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.class_init = nubus_class_init,
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};
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static void nubus_register_types(void)
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{
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type_register_static(&nubus_bus_info);
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}
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type_init(nubus_register_types)
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