415 lines
13 KiB
C
415 lines
13 KiB
C
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/*
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* QEMU PowerPC PowerNV Emulation of some SBE behaviour
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*
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* Copyright (c) 2022, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "target/ppc/cpu.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/pnv_sbe.h"
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#include "trace.h"
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/*
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* Most register and command definitions come from skiboot.
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*
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* xscom addresses are adjusted to be relative to xscom subregion bases
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*/
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/*
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* SBE MBOX register address
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* Reg 0 - 3 : Host to send command packets to SBE
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* Reg 4 - 7 : SBE to send response packets to Host
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*/
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#define PSU_HOST_SBE_MBOX_REG0 0x00000000
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#define PSU_HOST_SBE_MBOX_REG1 0x00000001
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#define PSU_HOST_SBE_MBOX_REG2 0x00000002
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#define PSU_HOST_SBE_MBOX_REG3 0x00000003
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#define PSU_HOST_SBE_MBOX_REG4 0x00000004
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#define PSU_HOST_SBE_MBOX_REG5 0x00000005
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#define PSU_HOST_SBE_MBOX_REG6 0x00000006
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#define PSU_HOST_SBE_MBOX_REG7 0x00000007
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#define PSU_SBE_DOORBELL_REG_RW 0x00000010
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#define PSU_SBE_DOORBELL_REG_AND 0x00000011
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#define PSU_SBE_DOORBELL_REG_OR 0x00000012
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#define PSU_HOST_DOORBELL_REG_RW 0x00000013
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#define PSU_HOST_DOORBELL_REG_AND 0x00000014
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#define PSU_HOST_DOORBELL_REG_OR 0x00000015
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/*
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* Doorbell register to trigger SBE interrupt. Set by OPAL to inform
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* the SBE about a waiting message in the Host/SBE mailbox registers
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*/
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#define HOST_SBE_MSG_WAITING PPC_BIT(0)
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/*
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* Doorbell register for host bridge interrupt. Set by the SBE to inform
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* host about a response message in the Host/SBE mailbox registers
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*/
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#define SBE_HOST_RESPONSE_WAITING PPC_BIT(0)
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#define SBE_HOST_MSG_READ PPC_BIT(1)
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#define SBE_HOST_STOP15_EXIT PPC_BIT(2)
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#define SBE_HOST_RESET PPC_BIT(3)
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#define SBE_HOST_PASSTHROUGH PPC_BIT(4)
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#define SBE_HOST_TIMER_EXPIRY PPC_BIT(14)
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#define SBE_HOST_RESPONSE_MASK (PPC_BITMASK(0, 4) | \
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SBE_HOST_TIMER_EXPIRY)
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/* SBE Control Register */
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#define SBE_CONTROL_REG_RW 0x00000000
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/* SBE interrupt s0/s1 bits */
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#define SBE_CONTROL_REG_S0 PPC_BIT(14)
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#define SBE_CONTROL_REG_S1 PPC_BIT(15)
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struct sbe_msg {
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uint64_t reg[4];
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};
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static uint64_t pnv_sbe_power9_xscom_ctrl_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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switch (offset) {
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default:
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qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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trace_pnv_sbe_xscom_ctrl_read(addr, val);
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return val;
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}
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static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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uint32_t offset = addr >> 3;
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trace_pnv_sbe_xscom_ctrl_write(addr, val);
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switch (offset) {
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default:
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qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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static const MemoryRegionOps pnv_sbe_power9_xscom_ctrl_ops = {
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.read = pnv_sbe_power9_xscom_ctrl_read,
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.write = pnv_sbe_power9_xscom_ctrl_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val)
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{
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val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW do? */
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sbe->host_doorbell = val;
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trace_pnv_sbe_reg_set_host_doorbell(val);
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qemu_set_irq(sbe->psi_irq, !!val);
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}
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/* SBE Target Type */
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#define SBE_TARGET_TYPE_PROC 0x00
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#define SBE_TARGET_TYPE_EX 0x01
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#define SBE_TARGET_TYPE_PERV 0x02
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#define SBE_TARGET_TYPE_MCS 0x03
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#define SBE_TARGET_TYPE_EQ 0x04
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#define SBE_TARGET_TYPE_CORE 0x05
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/* SBE MBOX command class */
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#define SBE_MCLASS_FIRST 0xD1
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#define SBE_MCLASS_CORE_STATE 0xD1
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#define SBE_MCLASS_SCOM 0xD2
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#define SBE_MCLASS_RING 0xD3
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#define SBE_MCLASS_TIMER 0xD4
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#define SBE_MCLASS_MPIPL 0xD5
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#define SBE_MCLASS_SECURITY 0xD6
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#define SBE_MCLASS_GENERIC 0xD7
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#define SBE_MCLASS_LAST 0xD7
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/*
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* Commands are provided in xxyy form where:
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* - xx : command class
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* - yy : command
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*
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* Both request and response message uses same seq ID,
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* command class and command.
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*/
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#define SBE_CMD_CTRL_DEADMAN_LOOP 0xD101
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#define SBE_CMD_MULTI_SCOM 0xD201
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#define SBE_CMD_PUT_RING_FORM_IMAGE 0xD301
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#define SBE_CMD_CONTROL_TIMER 0xD401
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#define SBE_CMD_GET_ARCHITECTED_REG 0xD501
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#define SBE_CMD_CLR_ARCHITECTED_REG 0xD502
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#define SBE_CMD_SET_UNSEC_MEM_WINDOW 0xD601
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#define SBE_CMD_GET_SBE_FFDC 0xD701
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#define SBE_CMD_GET_CAPABILITY 0xD702
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#define SBE_CMD_READ_SBE_SEEPROM 0xD703
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#define SBE_CMD_SET_FFDC_ADDR 0xD704
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#define SBE_CMD_QUIESCE_SBE 0xD705
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#define SBE_CMD_SET_FABRIC_ID_MAP 0xD706
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#define SBE_CMD_STASH_MPIPL_CONFIG 0xD707
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/* SBE MBOX control flags */
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/* Generic flags */
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#define SBE_CMD_CTRL_RESP_REQ 0x0100
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#define SBE_CMD_CTRL_ACK_REQ 0x0200
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/* Deadman loop */
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#define CTRL_DEADMAN_LOOP_START 0x0001
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#define CTRL_DEADMAN_LOOP_STOP 0x0002
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/* Control timer */
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#define CONTROL_TIMER_START 0x0001
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#define CONTROL_TIMER_STOP 0x0002
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/* Stash MPIPL config */
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#define SBE_STASH_KEY_SKIBOOT_BASE 0x03
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static void sbe_timer(void *opaque)
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{
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PnvSBE *sbe = opaque;
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trace_pnv_sbe_cmd_timer_expired();
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pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_TIMER_EXPIRY);
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}
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static void do_sbe_msg(PnvSBE *sbe)
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{
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struct sbe_msg msg;
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uint16_t cmd, ctrl_flags, seq_id;
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int i;
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memset(&msg, 0, sizeof(msg));
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for (i = 0; i < 4; i++) {
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msg.reg[i] = sbe->mbox[i];
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}
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cmd = msg.reg[0];
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seq_id = msg.reg[0] >> 16;
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ctrl_flags = msg.reg[0] >> 32;
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trace_pnv_sbe_msg_recv(cmd, seq_id, ctrl_flags);
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if (ctrl_flags & SBE_CMD_CTRL_ACK_REQ) {
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pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_MSG_READ);
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}
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switch (cmd) {
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case SBE_CMD_CONTROL_TIMER:
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if (ctrl_flags & CONTROL_TIMER_START) {
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uint64_t us = msg.reg[1];
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trace_pnv_sbe_cmd_timer_start(us);
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timer_mod(sbe->timer, qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) + us);
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}
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if (ctrl_flags & CONTROL_TIMER_STOP) {
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trace_pnv_sbe_cmd_timer_stop();
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timer_del(sbe->timer);
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command: 0x%x\n", cmd);
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}
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}
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static void pnv_sbe_set_sbe_doorbell(PnvSBE *sbe, uint64_t val)
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{
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val &= HOST_SBE_MSG_WAITING;
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sbe->sbe_doorbell = val;
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if (val & HOST_SBE_MSG_WAITING) {
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sbe->sbe_doorbell &= ~HOST_SBE_MSG_WAITING;
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do_sbe_msg(sbe);
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}
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}
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static uint64_t pnv_sbe_power9_xscom_mbox_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvSBE *sbe = PNV_SBE(opaque);
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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if (offset <= PSU_HOST_SBE_MBOX_REG7) {
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uint32_t idx = offset - PSU_HOST_SBE_MBOX_REG0;
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val = sbe->mbox[idx];
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} else {
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switch (offset) {
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case PSU_SBE_DOORBELL_REG_RW:
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val = sbe->sbe_doorbell;
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break;
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case PSU_HOST_DOORBELL_REG_RW:
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val = sbe->host_doorbell;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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trace_pnv_sbe_xscom_mbox_read(addr, val);
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return val;
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}
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static void pnv_sbe_power9_xscom_mbox_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvSBE *sbe = PNV_SBE(opaque);
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uint32_t offset = addr >> 3;
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trace_pnv_sbe_xscom_mbox_write(addr, val);
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if (offset <= PSU_HOST_SBE_MBOX_REG7) {
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uint32_t idx = offset - PSU_HOST_SBE_MBOX_REG0;
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sbe->mbox[idx] = val;
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} else {
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switch (offset) {
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case PSU_SBE_DOORBELL_REG_RW:
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pnv_sbe_set_sbe_doorbell(sbe, val);
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break;
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case PSU_SBE_DOORBELL_REG_AND:
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pnv_sbe_set_sbe_doorbell(sbe, sbe->sbe_doorbell & val);
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break;
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case PSU_SBE_DOORBELL_REG_OR:
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pnv_sbe_set_sbe_doorbell(sbe, sbe->sbe_doorbell | val);
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break;
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case PSU_HOST_DOORBELL_REG_RW:
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pnv_sbe_set_host_doorbell(sbe, val);
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break;
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case PSU_HOST_DOORBELL_REG_AND:
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pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell & val);
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break;
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case PSU_HOST_DOORBELL_REG_OR:
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pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | val);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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}
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static const MemoryRegionOps pnv_sbe_power9_xscom_mbox_ops = {
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.read = pnv_sbe_power9_xscom_mbox_read,
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.write = pnv_sbe_power9_xscom_mbox_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_sbe_power9_class_init(ObjectClass *klass, void *data)
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{
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PnvSBEClass *psc = PNV_SBE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "PowerNV SBE Controller (POWER9)";
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psc->xscom_ctrl_size = PNV9_XSCOM_SBE_CTRL_SIZE;
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psc->xscom_ctrl_ops = &pnv_sbe_power9_xscom_ctrl_ops;
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psc->xscom_mbox_size = PNV9_XSCOM_SBE_MBOX_SIZE;
|
||
|
|
psc->xscom_mbox_ops = &pnv_sbe_power9_xscom_mbox_ops;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo pnv_sbe_power9_type_info = {
|
||
|
|
.name = TYPE_PNV9_SBE,
|
||
|
|
.parent = TYPE_PNV_SBE,
|
||
|
|
.instance_size = sizeof(PnvSBE),
|
||
|
|
.class_init = pnv_sbe_power9_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void pnv_sbe_power10_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
PnvSBEClass *psc = PNV_SBE_CLASS(klass);
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->desc = "PowerNV SBE Controller (POWER10)";
|
||
|
|
psc->xscom_ctrl_size = PNV10_XSCOM_SBE_CTRL_SIZE;
|
||
|
|
psc->xscom_ctrl_ops = &pnv_sbe_power9_xscom_ctrl_ops;
|
||
|
|
psc->xscom_mbox_size = PNV10_XSCOM_SBE_MBOX_SIZE;
|
||
|
|
psc->xscom_mbox_ops = &pnv_sbe_power9_xscom_mbox_ops;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo pnv_sbe_power10_type_info = {
|
||
|
|
.name = TYPE_PNV10_SBE,
|
||
|
|
.parent = TYPE_PNV9_SBE,
|
||
|
|
.class_init = pnv_sbe_power10_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void pnv_sbe_realize(DeviceState *dev, Error **errp)
|
||
|
|
{
|
||
|
|
PnvSBE *sbe = PNV_SBE(dev);
|
||
|
|
PnvSBEClass *psc = PNV_SBE_GET_CLASS(sbe);
|
||
|
|
|
||
|
|
/* XScom regions for SBE registers */
|
||
|
|
pnv_xscom_region_init(&sbe->xscom_ctrl_regs, OBJECT(dev),
|
||
|
|
psc->xscom_ctrl_ops, sbe, "xscom-sbe-ctrl",
|
||
|
|
psc->xscom_ctrl_size);
|
||
|
|
pnv_xscom_region_init(&sbe->xscom_mbox_regs, OBJECT(dev),
|
||
|
|
psc->xscom_mbox_ops, sbe, "xscom-sbe-mbox",
|
||
|
|
psc->xscom_mbox_size);
|
||
|
|
|
||
|
|
qdev_init_gpio_out(DEVICE(dev), &sbe->psi_irq, 1);
|
||
|
|
|
||
|
|
sbe->timer = timer_new_us(QEMU_CLOCK_VIRTUAL, sbe_timer, sbe);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void pnv_sbe_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->realize = pnv_sbe_realize;
|
||
|
|
dc->desc = "PowerNV SBE Controller";
|
||
|
|
dc->user_creatable = false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo pnv_sbe_type_info = {
|
||
|
|
.name = TYPE_PNV_SBE,
|
||
|
|
.parent = TYPE_DEVICE,
|
||
|
|
.instance_size = sizeof(PnvSBE),
|
||
|
|
.class_init = pnv_sbe_class_init,
|
||
|
|
.class_size = sizeof(PnvSBEClass),
|
||
|
|
.abstract = true,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void pnv_sbe_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&pnv_sbe_type_info);
|
||
|
|
type_register_static(&pnv_sbe_power9_type_info);
|
||
|
|
type_register_static(&pnv_sbe_power10_type_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(pnv_sbe_register_types);
|