2020-10-17 00:27:46 +02:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Define i386 target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('a', 1u << TCG_REG_EAX)
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REGS('b', 1u << TCG_REG_EBX)
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REGS('c', 1u << TCG_REG_ECX)
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REGS('d', 1u << TCG_REG_EDX)
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REGS('S', 1u << TCG_REG_ESI)
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REGS('D', 1u << TCG_REG_EDI)
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REGS('r', ALL_GENERAL_REGS)
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REGS('x', ALL_VECTOR_REGS)
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REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
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REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */
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REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('e', TCG_CT_CONST_S32)
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CONST('I', TCG_CT_CONST_I32)
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2024-01-09 23:15:07 +01:00
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CONST('T', TCG_CT_CONST_TST)
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2020-10-17 00:27:46 +02:00
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CONST('W', TCG_CT_CONST_WSZ)
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CONST('Z', TCG_CT_CONST_U32)
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