2006-05-13 18:11:23 +02:00
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/*
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2007-10-29 00:42:18 +01:00
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* QEMU Grackle PCI host (heathrow OldWorld PowerMac)
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2006-05-13 18:11:23 +02:00
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*
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2007-10-29 00:42:18 +01:00
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* Copyright (c) 2006-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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2007-09-16 23:08:06 +02:00
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*
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2006-05-13 18:11:23 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 19:16:58 +01:00
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#include "qemu/osdep.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/mac.h"
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#include "hw/pci/pci.h"
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2018-03-06 23:01:55 +01:00
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#include "hw/intc/heathrow_pic.h"
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#include "qapi/error.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2018-01-26 10:20:27 +01:00
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#include "trace.h"
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2008-12-24 10:38:16 +01:00
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2012-08-20 19:08:00 +02:00
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#define GRACKLE_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(GrackleState, (obj), TYPE_GRACKLE_PCI_HOST_BRIDGE)
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2009-07-31 22:23:02 +02:00
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typedef struct GrackleState {
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2012-08-20 19:08:09 +02:00
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PCIHostState parent_obj;
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2012-08-20 19:08:00 +02:00
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2018-08-29 18:59:08 +02:00
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uint32_t ofw_addr;
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2018-03-06 23:01:55 +01:00
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HeathrowState *pic;
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qemu_irq irqs[4];
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2011-09-17 22:30:50 +02:00
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MemoryRegion pci_mmio;
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MemoryRegion pci_hole;
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2018-03-06 23:01:57 +01:00
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MemoryRegion pci_io;
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2009-07-31 22:23:02 +02:00
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} GrackleState;
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2006-05-13 18:11:23 +02:00
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2006-09-24 02:16:34 +02:00
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/* Don't know if this matches real hardware, but it agrees with OHW. */
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static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
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2006-05-13 18:11:23 +02:00
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{
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2006-09-24 02:16:34 +02:00
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return (irq_num + (pci_dev->devfn >> 3)) & 3;
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}
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2009-08-28 15:28:17 +02:00
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static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
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2006-09-24 02:16:34 +02:00
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{
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2018-03-06 23:01:55 +01:00
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GrackleState *s = opaque;
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2009-08-28 15:28:17 +02:00
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2018-01-26 10:20:27 +01:00
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trace_grackle_set_irq(irq_num, level);
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2018-03-06 23:01:55 +01:00
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qemu_set_irq(s->irqs[irq_num], level);
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2006-05-13 18:11:23 +02:00
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}
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2018-03-06 23:01:55 +01:00
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static void grackle_init_irqs(GrackleState *s)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
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s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), 0x15 + i);
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}
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}
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static void grackle_realize(DeviceState *dev, Error **errp)
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{
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GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
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PCIHostState *phb = PCI_HOST_BRIDGE(dev);
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2017-11-29 09:46:22 +01:00
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phb->bus = pci_register_root_bus(dev, NULL,
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pci_grackle_set_irq,
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pci_grackle_map_irq,
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2018-03-06 23:01:55 +01:00
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s,
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&s->pci_mmio,
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2018-03-06 23:01:57 +01:00
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&s->pci_io,
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2017-11-29 09:46:22 +01:00
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0, 4, TYPE_PCI_BUS);
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2009-07-31 22:23:02 +02:00
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2012-08-20 19:08:00 +02:00
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pci_create_simple(phb->bus, 0, "grackle");
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2018-03-06 23:01:55 +01:00
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grackle_init_irqs(s);
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2009-07-31 22:23:02 +02:00
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}
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2018-03-06 23:01:55 +01:00
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static void grackle_init(Object *obj)
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2009-07-31 22:23:02 +02:00
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{
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2018-03-06 23:01:55 +01:00
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GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *phb = PCI_HOST_BRIDGE(obj);
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2009-07-31 22:23:02 +02:00
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2018-03-06 23:01:55 +01:00
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memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
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2018-03-06 23:01:57 +01:00
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memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
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"pci-isa-mmio", 0x00200000);
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2018-03-06 23:01:55 +01:00
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memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio,
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0x80000000ULL, 0x7e000000ULL);
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2009-07-31 22:23:02 +02:00
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2018-03-06 23:01:55 +01:00
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memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops,
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DEVICE(obj), "pci-conf-idx", 0x1000);
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memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops,
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DEVICE(obj), "pci-data-idx", 0x1000);
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2009-07-31 22:23:02 +02:00
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2018-03-06 23:01:55 +01:00
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object_property_add_link(obj, "pic", TYPE_HEATHROW,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0, NULL);
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sysbus_init_mmio(sbd, &phb->conf_mem);
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sysbus_init_mmio(sbd, &phb->data_mem);
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2018-03-06 23:01:56 +01:00
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sysbus_init_mmio(sbd, &s->pci_hole);
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2018-03-06 23:01:57 +01:00
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sysbus_init_mmio(sbd, &s->pci_io);
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2009-07-31 22:23:02 +02:00
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}
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2018-03-06 23:01:55 +01:00
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static void grackle_pci_realize(PCIDevice *d, Error **errp)
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2009-07-31 22:23:02 +02:00
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{
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2006-05-13 18:11:23 +02:00
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d->config[0x09] = 0x01;
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2009-07-31 22:23:02 +02:00
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}
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2006-05-13 18:11:23 +02:00
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2011-12-04 19:22:06 +01:00
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static void grackle_pci_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 04:34:16 +01:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2018-03-06 23:01:55 +01:00
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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2011-12-04 19:22:06 +01:00
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2018-03-06 23:01:55 +01:00
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k->realize = grackle_pci_realize;
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2011-12-04 19:22:06 +01:00
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k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
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k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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2017-05-03 22:35:44 +02:00
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dc->user_creatable = false;
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2011-12-04 19:22:06 +01:00
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}
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2012-08-20 19:07:56 +02:00
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static const TypeInfo grackle_pci_info = {
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2011-12-08 04:34:16 +01:00
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.name = "grackle",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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2011-12-04 19:22:06 +01:00
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.class_init = grackle_pci_class_init,
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2017-09-27 21:56:34 +02:00
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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2009-07-31 22:23:02 +02:00
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};
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2008-12-28 19:27:10 +01:00
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2018-08-29 18:59:08 +02:00
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static char *grackle_ofw_unit_address(const SysBusDevice *dev)
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{
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GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
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return g_strdup_printf("%x", s->ofw_addr);
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}
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static Property grackle_properties[] = {
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DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1),
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DEFINE_PROP_END_OF_LIST()
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};
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2018-03-06 23:01:55 +01:00
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static void grackle_class_init(ObjectClass *klass, void *data)
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2012-01-24 20:12:29 +01:00
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{
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2015-09-26 18:22:06 +02:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2018-08-29 18:59:08 +02:00
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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2012-01-24 20:12:29 +01:00
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2018-03-06 23:01:55 +01:00
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dc->realize = grackle_realize;
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2018-08-29 18:59:08 +02:00
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dc->props = grackle_properties;
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2015-09-26 18:22:06 +02:00
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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2018-08-29 18:59:08 +02:00
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dc->fw_name = "pci";
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sbc->explicit_ofw_unit_address = grackle_ofw_unit_address;
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2012-01-24 20:12:29 +01:00
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}
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2018-03-06 23:01:55 +01:00
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static const TypeInfo grackle_host_info = {
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2012-08-20 19:08:00 +02:00
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.name = TYPE_GRACKLE_PCI_HOST_BRIDGE,
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2012-08-20 19:08:08 +02:00
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.parent = TYPE_PCI_HOST_BRIDGE,
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2011-12-08 04:34:16 +01:00
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.instance_size = sizeof(GrackleState),
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2018-03-06 23:01:55 +01:00
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.instance_init = grackle_init,
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.class_init = grackle_class_init,
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2012-01-18 01:11:16 +01:00
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};
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2012-02-09 15:20:55 +01:00
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static void grackle_register_types(void)
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2009-07-31 22:23:02 +02:00
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{
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2011-12-08 04:34:16 +01:00
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type_register_static(&grackle_pci_info);
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2018-03-06 23:01:55 +01:00
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type_register_static(&grackle_host_info);
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2006-05-13 18:11:23 +02:00
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}
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2009-07-31 22:23:02 +02:00
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2012-02-09 15:20:55 +01:00
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type_init(grackle_register_types)
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