519 lines
11 KiB
C
519 lines
11 KiB
C
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/*
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* Helpers for CWP and PSTATE handling
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "dyngen-exec.h"
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#include "helper.h"
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//#define DEBUG_PSTATE
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#ifdef DEBUG_PSTATE
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#define DPRINTF_PSTATE(fmt, ...) \
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do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
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#endif
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static inline void memcpy32(target_ulong *dst, const target_ulong *src)
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{
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dst[0] = src[0];
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dst[1] = src[1];
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dst[2] = src[2];
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dst[3] = src[3];
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dst[4] = src[4];
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dst[5] = src[5];
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dst[6] = src[6];
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dst[7] = src[7];
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}
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static void set_cwp(int new_cwp)
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{
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/* put the modified wrap registers at their proper location */
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if (env->cwp == env->nwindows - 1) {
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memcpy32(env->regbase, env->regbase + env->nwindows * 16);
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}
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env->cwp = new_cwp;
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/* put the wrap registers at their temporary location */
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if (new_cwp == env->nwindows - 1) {
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memcpy32(env->regbase + env->nwindows * 16, env->regbase);
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}
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env->regwptr = env->regbase + (new_cwp * 16);
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}
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void cpu_set_cwp(CPUState *env1, int new_cwp)
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{
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CPUState *saved_env;
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saved_env = env;
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env = env1;
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set_cwp(new_cwp);
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env = saved_env;
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}
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static target_ulong get_psr(void)
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{
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helper_compute_psr(env);
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#if !defined(TARGET_SPARC64)
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return env->version | (env->psr & PSR_ICC) |
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(env->psref ? PSR_EF : 0) |
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(env->psrpil << 8) |
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(env->psrs ? PSR_S : 0) |
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(env->psrps ? PSR_PS : 0) |
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(env->psret ? PSR_ET : 0) | env->cwp;
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#else
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return env->psr & PSR_ICC;
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#endif
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}
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target_ulong cpu_get_psr(CPUState *env1)
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{
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CPUState *saved_env;
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target_ulong ret;
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saved_env = env;
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env = env1;
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ret = get_psr();
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env = saved_env;
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return ret;
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}
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static void put_psr(target_ulong val)
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{
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env->psr = val & PSR_ICC;
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#if !defined(TARGET_SPARC64)
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env->psref = (val & PSR_EF) ? 1 : 0;
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env->psrpil = (val & PSR_PIL) >> 8;
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#endif
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#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
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cpu_check_irqs(env);
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#endif
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#if !defined(TARGET_SPARC64)
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env->psrs = (val & PSR_S) ? 1 : 0;
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env->psrps = (val & PSR_PS) ? 1 : 0;
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env->psret = (val & PSR_ET) ? 1 : 0;
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set_cwp(val & PSR_CWP);
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#endif
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env->cc_op = CC_OP_FLAGS;
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}
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void cpu_put_psr(CPUState *env1, target_ulong val)
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{
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CPUState *saved_env;
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saved_env = env;
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env = env1;
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put_psr(val);
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env = saved_env;
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}
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static int cwp_inc(int cwp)
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{
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if (unlikely(cwp >= env->nwindows)) {
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cwp -= env->nwindows;
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}
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return cwp;
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}
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int cpu_cwp_inc(CPUState *env1, int cwp)
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{
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CPUState *saved_env;
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target_ulong ret;
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saved_env = env;
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env = env1;
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ret = cwp_inc(cwp);
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env = saved_env;
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return ret;
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}
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static int cwp_dec(int cwp)
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{
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if (unlikely(cwp < 0)) {
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cwp += env->nwindows;
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}
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return cwp;
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}
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int cpu_cwp_dec(CPUState *env1, int cwp)
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{
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CPUState *saved_env;
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target_ulong ret;
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saved_env = env;
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env = env1;
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ret = cwp_dec(cwp);
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env = saved_env;
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return ret;
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}
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#ifndef TARGET_SPARC64
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void helper_rett(void)
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{
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unsigned int cwp;
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if (env->psret == 1) {
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helper_raise_exception(env, TT_ILL_INSN);
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}
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env->psret = 1;
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cwp = cwp_inc(env->cwp + 1) ;
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if (env->wim & (1 << cwp)) {
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helper_raise_exception(env, TT_WIN_UNF);
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}
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set_cwp(cwp);
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env->psrs = env->psrps;
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}
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/* XXX: use another pointer for %iN registers to avoid slow wrapping
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handling ? */
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void helper_save(void)
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{
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uint32_t cwp;
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cwp = cwp_dec(env->cwp - 1);
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if (env->wim & (1 << cwp)) {
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helper_raise_exception(env, TT_WIN_OVF);
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}
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set_cwp(cwp);
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}
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void helper_restore(void)
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{
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uint32_t cwp;
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cwp = cwp_inc(env->cwp + 1);
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if (env->wim & (1 << cwp)) {
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helper_raise_exception(env, TT_WIN_UNF);
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}
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set_cwp(cwp);
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}
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void helper_wrpsr(target_ulong new_psr)
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{
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if ((new_psr & PSR_CWP) >= env->nwindows) {
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helper_raise_exception(env, TT_ILL_INSN);
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} else {
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cpu_put_psr(env, new_psr);
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}
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}
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target_ulong helper_rdpsr(void)
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{
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return get_psr();
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}
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#else
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/* XXX: use another pointer for %iN registers to avoid slow wrapping
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handling ? */
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void helper_save(void)
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{
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uint32_t cwp;
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cwp = cwp_dec(env->cwp - 1);
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if (env->cansave == 0) {
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helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
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(TT_WOTHER |
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((env->wstate & 0x38) >> 1)) :
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((env->wstate & 0x7) << 2)));
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} else {
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if (env->cleanwin - env->canrestore == 0) {
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/* XXX Clean windows without trap */
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helper_raise_exception(env, TT_CLRWIN);
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} else {
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env->cansave--;
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env->canrestore++;
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set_cwp(cwp);
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}
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}
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}
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void helper_restore(void)
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{
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uint32_t cwp;
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cwp = cwp_inc(env->cwp + 1);
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if (env->canrestore == 0) {
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helper_raise_exception(env, TT_FILL | (env->otherwin != 0 ?
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(TT_WOTHER |
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((env->wstate & 0x38) >> 1)) :
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((env->wstate & 0x7) << 2)));
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} else {
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env->cansave++;
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env->canrestore--;
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set_cwp(cwp);
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}
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}
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void helper_flushw(void)
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{
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if (env->cansave != env->nwindows - 2) {
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helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
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(TT_WOTHER |
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((env->wstate & 0x38) >> 1)) :
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((env->wstate & 0x7) << 2)));
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}
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}
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void helper_saved(void)
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{
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env->cansave++;
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if (env->otherwin == 0) {
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env->canrestore--;
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} else {
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env->otherwin--;
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}
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}
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void helper_restored(void)
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{
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env->canrestore++;
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if (env->cleanwin < env->nwindows - 1) {
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env->cleanwin++;
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}
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if (env->otherwin == 0) {
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env->cansave--;
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} else {
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env->otherwin--;
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}
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}
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static target_ulong get_ccr(void)
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{
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target_ulong psr;
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psr = get_psr();
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return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
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}
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target_ulong cpu_get_ccr(CPUState *env1)
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{
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CPUState *saved_env;
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target_ulong ret;
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saved_env = env;
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env = env1;
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ret = get_ccr();
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env = saved_env;
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return ret;
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}
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static void put_ccr(target_ulong val)
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{
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env->xcc = (val >> 4) << 20;
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env->psr = (val & 0xf) << 20;
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CC_OP = CC_OP_FLAGS;
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}
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void cpu_put_ccr(CPUState *env1, target_ulong val)
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{
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CPUState *saved_env;
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saved_env = env;
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env = env1;
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put_ccr(val);
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env = saved_env;
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}
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static target_ulong get_cwp64(void)
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{
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return env->nwindows - 1 - env->cwp;
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}
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target_ulong cpu_get_cwp64(CPUState *env1)
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{
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CPUState *saved_env;
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target_ulong ret;
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saved_env = env;
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env = env1;
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ret = get_cwp64();
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env = saved_env;
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return ret;
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}
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static void put_cwp64(int cwp)
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{
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if (unlikely(cwp >= env->nwindows || cwp < 0)) {
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cwp %= env->nwindows;
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}
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set_cwp(env->nwindows - 1 - cwp);
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}
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void cpu_put_cwp64(CPUState *env1, int cwp)
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{
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CPUState *saved_env;
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saved_env = env;
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env = env1;
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put_cwp64(cwp);
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env = saved_env;
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}
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target_ulong helper_rdccr(void)
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{
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return get_ccr();
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}
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void helper_wrccr(target_ulong new_ccr)
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{
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put_ccr(new_ccr);
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}
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/* CWP handling is reversed in V9, but we still use the V8 register
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order. */
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target_ulong helper_rdcwp(void)
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{
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return get_cwp64();
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}
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void helper_wrcwp(target_ulong new_cwp)
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{
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put_cwp64(new_cwp);
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}
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static inline uint64_t *get_gregset(uint32_t pstate)
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{
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switch (pstate) {
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default:
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DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
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pstate,
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(pstate & PS_IG) ? " IG" : "",
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(pstate & PS_MG) ? " MG" : "",
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(pstate & PS_AG) ? " AG" : "");
|
||
|
|
/* pass through to normal set of global registers */
|
||
|
|
case 0:
|
||
|
|
return env->bgregs;
|
||
|
|
case PS_AG:
|
||
|
|
return env->agregs;
|
||
|
|
case PS_MG:
|
||
|
|
return env->mgregs;
|
||
|
|
case PS_IG:
|
||
|
|
return env->igregs;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void change_pstate(uint32_t new_pstate)
|
||
|
|
{
|
||
|
|
uint32_t pstate_regs, new_pstate_regs;
|
||
|
|
uint64_t *src, *dst;
|
||
|
|
|
||
|
|
if (env->def->features & CPU_FEATURE_GL) {
|
||
|
|
/* PS_AG is not implemented in this case */
|
||
|
|
new_pstate &= ~PS_AG;
|
||
|
|
}
|
||
|
|
|
||
|
|
pstate_regs = env->pstate & 0xc01;
|
||
|
|
new_pstate_regs = new_pstate & 0xc01;
|
||
|
|
|
||
|
|
if (new_pstate_regs != pstate_regs) {
|
||
|
|
DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
|
||
|
|
pstate_regs, new_pstate_regs);
|
||
|
|
/* Switch global register bank */
|
||
|
|
src = get_gregset(new_pstate_regs);
|
||
|
|
dst = get_gregset(pstate_regs);
|
||
|
|
memcpy32(dst, env->gregs);
|
||
|
|
memcpy32(env->gregs, src);
|
||
|
|
} else {
|
||
|
|
DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
|
||
|
|
new_pstate_regs);
|
||
|
|
}
|
||
|
|
env->pstate = new_pstate;
|
||
|
|
}
|
||
|
|
|
||
|
|
void helper_wrpstate(target_ulong new_state)
|
||
|
|
{
|
||
|
|
change_pstate(new_state & 0xf3f);
|
||
|
|
|
||
|
|
#if !defined(CONFIG_USER_ONLY)
|
||
|
|
if (cpu_interrupts_enabled(env)) {
|
||
|
|
cpu_check_irqs(env);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_change_pstate(CPUState *env1, uint32_t new_pstate)
|
||
|
|
{
|
||
|
|
CPUState *saved_env;
|
||
|
|
|
||
|
|
saved_env = env;
|
||
|
|
env = env1;
|
||
|
|
change_pstate(new_pstate);
|
||
|
|
env = saved_env;
|
||
|
|
}
|
||
|
|
|
||
|
|
void helper_wrpil(target_ulong new_pil)
|
||
|
|
{
|
||
|
|
#if !defined(CONFIG_USER_ONLY)
|
||
|
|
DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
|
||
|
|
env->psrpil, (uint32_t)new_pil);
|
||
|
|
|
||
|
|
env->psrpil = new_pil;
|
||
|
|
|
||
|
|
if (cpu_interrupts_enabled(env)) {
|
||
|
|
cpu_check_irqs(env);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void helper_done(void)
|
||
|
|
{
|
||
|
|
trap_state *tsptr = cpu_tsptr(env);
|
||
|
|
|
||
|
|
env->pc = tsptr->tnpc;
|
||
|
|
env->npc = tsptr->tnpc + 4;
|
||
|
|
put_ccr(tsptr->tstate >> 32);
|
||
|
|
env->asi = (tsptr->tstate >> 24) & 0xff;
|
||
|
|
change_pstate((tsptr->tstate >> 8) & 0xf3f);
|
||
|
|
put_cwp64(tsptr->tstate & 0xff);
|
||
|
|
env->tl--;
|
||
|
|
|
||
|
|
DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
|
||
|
|
|
||
|
|
#if !defined(CONFIG_USER_ONLY)
|
||
|
|
if (cpu_interrupts_enabled(env)) {
|
||
|
|
cpu_check_irqs(env);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void helper_retry(void)
|
||
|
|
{
|
||
|
|
trap_state *tsptr = cpu_tsptr(env);
|
||
|
|
|
||
|
|
env->pc = tsptr->tpc;
|
||
|
|
env->npc = tsptr->tnpc;
|
||
|
|
put_ccr(tsptr->tstate >> 32);
|
||
|
|
env->asi = (tsptr->tstate >> 24) & 0xff;
|
||
|
|
change_pstate((tsptr->tstate >> 8) & 0xf3f);
|
||
|
|
put_cwp64(tsptr->tstate & 0xff);
|
||
|
|
env->tl--;
|
||
|
|
|
||
|
|
DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
|
||
|
|
|
||
|
|
#if !defined(CONFIG_USER_ONLY)
|
||
|
|
if (cpu_interrupts_enabled(env)) {
|
||
|
|
cpu_check_irqs(env);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|