297 lines
11 KiB
C
297 lines
11 KiB
C
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/*
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* Altera Nios II MMU emulation for qemu.
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*
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* Copyright (C) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "mmu.h"
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#if !defined(CONFIG_USER_ONLY)
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/* Define this to enable MMU debug messages */
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/* #define DEBUG_MMU */
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#ifdef DEBUG_MMU
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#define MMU_LOG(x) x
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#else
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#define MMU_LOG(x)
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#endif
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void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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int ret;
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ret = nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
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if (unlikely(ret)) {
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if (retaddr) {
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr);
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}
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cpu_loop_exit(cs);
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}
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}
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void mmu_read_debug(CPUNios2State *env, uint32_t rn)
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{
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switch (rn) {
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case CR_TLBACC:
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MMU_LOG(qemu_log("TLBACC READ %08X\n", env->regs[rn]));
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break;
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case CR_TLBMISC:
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MMU_LOG(qemu_log("TLBMISC READ %08X\n", env->regs[rn]));
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break;
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case CR_PTEADDR:
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MMU_LOG(qemu_log("PTEADDR READ %08X\n", env->regs[rn]));
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break;
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default:
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break;
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}
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}
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/* rw - 0 = read, 1 = write, 2 = fetch. */
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unsigned int mmu_translate(CPUNios2State *env,
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Nios2MMULookup *lu,
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target_ulong vaddr, int rw, int mmu_idx)
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{
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int vpn = vaddr >> 12;
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MMU_LOG(qemu_log("mmu_translate vaddr %08X, pid %08X, vpn %08X\n",
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vaddr, pid, vpn));
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int way;
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for (way = 0; way < cpu->tlb_num_ways; way++) {
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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MMU_LOG(qemu_log("TLB[%d] TAG %08X, VPN %08X\n",
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(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask),
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entry->tag, (entry->tag >> 12)));
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if (((entry->tag >> 12) != vpn) ||
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(((entry->tag & (1 << 11)) == 0) &&
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) != pid))) {
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continue;
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}
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lu->vaddr = vaddr & TARGET_PAGE_MASK;
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lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
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lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) |
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((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) |
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((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);
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MMU_LOG(qemu_log("HIT TLB[%d] %08X %08X %08X\n",
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(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask),
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lu->vaddr, lu->paddr, lu->prot));
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return 1;
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}
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return 0;
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}
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static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
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{
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CPUState *cs = ENV_GET_CPU(env);
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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int idx;
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MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
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for (idx = 0; idx < cpu->tlb_num_entries; idx++) {
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Nios2TLBEntry *entry = &env->mmu.tlb[idx];
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MMU_LOG(qemu_log("TLB[%d] => %08X %08X\n",
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idx, entry->tag, entry->data));
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if ((entry->tag & (1 << 10)) && (!(entry->tag & (1 << 11))) &&
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) == pid)) {
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uint32_t vaddr = entry->tag & TARGET_PAGE_MASK;
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MMU_LOG(qemu_log("TLB Flush Page %08X\n", vaddr));
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tlb_flush_page(cs, vaddr);
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}
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}
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}
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void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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{
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CPUState *cs = ENV_GET_CPU(env);
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
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switch (rn) {
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case CR_TLBACC:
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MMU_LOG(qemu_log("TLBACC: IG %02X, FLAGS %c%c%c%c%c, PFN %05X\n",
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v >> CR_TLBACC_IGN_SHIFT,
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(v & CR_TLBACC_C) ? 'C' : '.',
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(v & CR_TLBACC_R) ? 'R' : '.',
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(v & CR_TLBACC_W) ? 'W' : '.',
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(v & CR_TLBACC_X) ? 'X' : '.',
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(v & CR_TLBACC_G) ? 'G' : '.',
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v & CR_TLBACC_PFN_MASK));
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/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
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if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
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int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
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int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int g = (v & CR_TLBACC_G) ? 1 : 0;
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int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid;
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uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W |
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CR_TLBACC_X | CR_TLBACC_PFN_MASK);
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if ((entry->tag != newTag) || (entry->data != newData)) {
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if (entry->tag & (1 << 10)) {
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/* Flush existing entry */
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MMU_LOG(qemu_log("TLB Flush Page (OLD) %08X\n",
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entry->tag & TARGET_PAGE_MASK));
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tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
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}
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entry->tag = newTag;
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entry->data = newData;
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MMU_LOG(qemu_log("TLB[%d] = %08X %08X\n",
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(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask),
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entry->tag, entry->data));
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}
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/* Auto-increment tlbmisc.WAY */
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env->regs[CR_TLBMISC] =
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(env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
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(((way + 1) & (cpu->tlb_num_ways - 1)) <<
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CR_TLBMISC_WAY_SHIFT);
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}
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/* Writes to TLBACC don't change the read-back value */
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env->mmu.tlbacc_wr = v;
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break;
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case CR_TLBMISC:
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MMU_LOG(qemu_log("TLBMISC: WAY %X, FLAGS %c%c%c%c%c%c, PID %04X\n",
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v >> CR_TLBMISC_WAY_SHIFT,
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(v & CR_TLBMISC_RD) ? 'R' : '.',
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(v & CR_TLBMISC_WR) ? 'W' : '.',
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(v & CR_TLBMISC_DBL) ? '2' : '.',
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(v & CR_TLBMISC_BAD) ? 'B' : '.',
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(v & CR_TLBMISC_PERM) ? 'P' : '.',
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(v & CR_TLBMISC_D) ? 'D' : '.',
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(v & CR_TLBMISC_PID_MASK) >> 4));
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if ((v & CR_TLBMISC_PID_MASK) !=
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(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
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mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
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CR_TLBMISC_PID_SHIFT);
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}
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/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
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if (v & CR_TLBMISC_RD) {
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int way = (v >> CR_TLBMISC_WAY_SHIFT);
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int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
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env->regs[CR_TLBACC] |= entry->data;
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env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
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env->regs[CR_TLBMISC] =
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(v & ~CR_TLBMISC_PID_MASK) |
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
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CR_TLBMISC_PID_SHIFT);
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env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
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env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
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MMU_LOG(qemu_log("TLB READ way %d, vpn %05X, tag %08X, data %08X, "
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"tlbacc %08X, tlbmisc %08X, pteaddr %08X\n",
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way, vpn, entry->tag, entry->data,
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env->regs[CR_TLBACC], env->regs[CR_TLBMISC],
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env->regs[CR_PTEADDR]));
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} else {
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env->regs[CR_TLBMISC] = v;
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}
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env->mmu.tlbmisc_wr = v;
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break;
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case CR_PTEADDR:
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MMU_LOG(qemu_log("PTEADDR: PTBASE %03X, VPN %05X\n",
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v >> CR_PTEADDR_PTBASE_SHIFT,
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(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT));
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/* Writes to PTEADDR don't change the read-back VPN value */
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env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
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(env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK);
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env->mmu.pteaddr_wr = v;
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break;
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default:
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break;
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}
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}
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void mmu_init(CPUNios2State *env)
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{
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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Nios2MMU *mmu = &env->mmu;
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MMU_LOG(qemu_log("mmu_init\n"));
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mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1;
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mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env)
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{
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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int i;
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cpu_fprintf(f, "MMU: ways %d, entries %d, pid bits %d\n",
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cpu->tlb_num_ways, cpu->tlb_num_entries,
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cpu->pid_num_bits);
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for (i = 0; i < cpu->tlb_num_entries; i++) {
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Nios2TLBEntry *entry = &env->mmu.tlb[i];
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cpu_fprintf(f, "TLB[%d] = %08X %08X %c VPN %05X "
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"PID %02X %c PFN %05X %c%c%c%c\n",
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i, entry->tag, entry->data,
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(entry->tag & (1 << 10)) ? 'V' : '-',
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entry->tag >> 12,
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entry->tag & ((1 << cpu->pid_num_bits) - 1),
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(entry->tag & (1 << 11)) ? 'G' : '-',
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entry->data & CR_TLBACC_PFN_MASK,
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(entry->data & CR_TLBACC_C) ? 'C' : '-',
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(entry->data & CR_TLBACC_R) ? 'R' : '-',
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(entry->data & CR_TLBACC_W) ? 'W' : '-',
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(entry->data & CR_TLBACC_X) ? 'X' : '-');
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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