289 lines
9.1 KiB
C
289 lines
9.1 KiB
C
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/*
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* MIPS emulation load/store helpers for QEMU.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/memop.h"
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#include "internal.h"
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#ifndef CONFIG_USER_ONLY
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#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
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target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
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{ \
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if (arg & almask) { \
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if (!(env->hflags & MIPS_HFLAG_DM)) { \
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env->CP0_BadVAddr = arg; \
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} \
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do_raise_exception(env, EXCP_AdEL, GETPC()); \
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} \
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env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \
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GETPC()); \
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env->lladdr = arg; \
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env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
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return env->llval; \
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}
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HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
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#ifdef TARGET_MIPS64
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HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
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#endif
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#undef HELPER_LD_ATOMIC
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#endif /* !CONFIG_USER_ONLY */
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK(v) ((v) & 3)
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#define GET_OFFSET(addr, offset) (addr + (offset))
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#else
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#define GET_LMASK(v) (((v) & 3) ^ 3)
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#define GET_OFFSET(addr, offset) (addr - (offset))
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#endif
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void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
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int mem_idx)
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{
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cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
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if (GET_LMASK(arg2) <= 2) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
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mem_idx, GETPC());
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}
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if (GET_LMASK(arg2) <= 1) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
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mem_idx, GETPC());
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}
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if (GET_LMASK(arg2) == 0) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
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mem_idx, GETPC());
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}
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}
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void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
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int mem_idx)
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{
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cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
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if (GET_LMASK(arg2) >= 1) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
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mem_idx, GETPC());
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}
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if (GET_LMASK(arg2) >= 2) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
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mem_idx, GETPC());
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}
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if (GET_LMASK(arg2) == 3) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
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mem_idx, GETPC());
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}
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}
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#if defined(TARGET_MIPS64)
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/*
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* "half" load and stores. We must do the memory access inline,
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* or fault handling won't work.
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*/
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK64(v) ((v) & 7)
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#else
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#define GET_LMASK64(v) (((v) & 7) ^ 7)
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#endif
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void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
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int mem_idx)
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{
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cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
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if (GET_LMASK64(arg2) <= 6) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) <= 5) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) <= 4) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) <= 3) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) <= 2) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) <= 1) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) <= 0) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
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mem_idx, GETPC());
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}
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}
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void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
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int mem_idx)
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{
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cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
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if (GET_LMASK64(arg2) >= 1) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) >= 2) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) >= 3) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) >= 4) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) >= 5) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) >= 6) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
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mem_idx, GETPC());
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}
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if (GET_LMASK64(arg2) == 7) {
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cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
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mem_idx, GETPC());
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}
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}
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#endif /* TARGET_MIPS64 */
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static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
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void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
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uint32_t mem_idx)
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{
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target_ulong base_reglist = reglist & 0xf;
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target_ulong do_r31 = reglist & 0x10;
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if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
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target_ulong i;
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for (i = 0; i < base_reglist; i++) {
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env->active_tc.gpr[multiple_regs[i]] =
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(target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
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addr += 4;
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}
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}
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if (do_r31) {
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env->active_tc.gpr[31] =
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(target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
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}
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}
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void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
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uint32_t mem_idx)
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{
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target_ulong base_reglist = reglist & 0xf;
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target_ulong do_r31 = reglist & 0x10;
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if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
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target_ulong i;
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for (i = 0; i < base_reglist; i++) {
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cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
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mem_idx, GETPC());
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addr += 4;
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}
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}
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if (do_r31) {
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cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
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}
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}
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#if defined(TARGET_MIPS64)
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void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
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uint32_t mem_idx)
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{
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target_ulong base_reglist = reglist & 0xf;
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target_ulong do_r31 = reglist & 0x10;
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if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
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target_ulong i;
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for (i = 0; i < base_reglist; i++) {
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env->active_tc.gpr[multiple_regs[i]] =
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cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
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addr += 8;
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}
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}
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if (do_r31) {
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env->active_tc.gpr[31] =
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cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
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}
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}
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void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
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uint32_t mem_idx)
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{
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target_ulong base_reglist = reglist & 0xf;
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target_ulong do_r31 = reglist & 0x10;
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if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
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target_ulong i;
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for (i = 0; i < base_reglist; i++) {
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cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
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mem_idx, GETPC());
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addr += 8;
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}
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}
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if (do_r31) {
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cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
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}
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}
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#endif /* TARGET_MIPS64 */
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