2013-12-17 20:42:30 +01:00
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/*
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* ARM implementation of KVM hooks, 64 bit specific code
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*
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* Copyright Mian-M. Hamayun 2013, Virtual Open Systems
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2015-12-17 14:37:15 +01:00
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* Copyright Alex Bennée 2014, Linaro
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2013-12-17 20:42:30 +01:00
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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2015-12-07 17:23:44 +01:00
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#include "qemu/osdep.h"
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2013-12-17 20:42:30 +01:00
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#include <sys/ioctl.h>
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2015-12-17 14:37:15 +01:00
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#include <sys/ptrace.h>
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2013-12-17 20:42:30 +01:00
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2015-12-17 14:37:15 +01:00
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#include <linux/elf.h>
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2013-12-17 20:42:30 +01:00
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#include <linux/kvm.h>
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2020-10-01 08:17:18 +02:00
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#include "qapi/error.h"
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2016-03-15 16:58:45 +01:00
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#include "cpu.h"
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2013-12-17 20:42:30 +01:00
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#include "qemu/timer.h"
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2015-12-17 14:37:15 +01:00
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#include "qemu/error-report.h"
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2015-12-17 14:37:15 +01:00
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#include "qemu/host-utils.h"
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Include qemu/main-loop.h less
In my "build everything" tree, changing qemu/main-loop.h triggers a
recompile of some 5600 out of 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h). It includes block/aio.h,
which in turn includes qemu/event_notifier.h, qemu/notify.h,
qemu/processor.h, qemu/qsp.h, qemu/queue.h, qemu/thread-posix.h,
qemu/thread.h, qemu/timer.h, and a few more.
Include qemu/main-loop.h only where it's needed. Touching it now
recompiles only some 1700 objects. For block/aio.h and
qemu/event_notifier.h, these numbers drop from 5600 to 2800. For the
others, they shrink only slightly.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20190812052359.30071-21-armbru@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-08-12 07:23:50 +02:00
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#include "qemu/main-loop.h"
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2015-12-17 14:37:15 +01:00
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#include "exec/gdbstub.h"
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2020-01-30 17:02:06 +01:00
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#include "sysemu/runstate.h"
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2013-12-17 20:42:30 +01:00
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#include "sysemu/kvm.h"
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2019-08-02 14:25:26 +02:00
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#include "sysemu/kvm_int.h"
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2013-12-17 20:42:30 +01:00
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#include "kvm_arm.h"
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2014-08-04 15:41:54 +02:00
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#include "internals.h"
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target-arm: kvm64: handle SIGBUS signal from kernel or KVM
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
External Abort(SEA). Then host kernel gets an APEI notification and calls
memory_failure() to unmapped the affected page in stage 2, finally
returns to guest.
Guest continues to access the PG_hwpoison page, it will trap to KVM as
stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
Qemu, Qemu records this error address into guest APEI GHES memory and
notifes guest using Synchronous-External-Abort(SEA).
In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function
in which we can setup the type of exception and the syndrome information.
When switching to guest, the target vcpu will jump to the synchronous
external abort vector table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the
ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
not valid and hold an UNKNOWN value. These values will be set to KVM
register structures through KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20200512030609.19593-10-gengdongjiu@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-12 05:06:08 +02:00
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/ghes.h"
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#include "hw/arm/virt.h"
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2013-12-17 20:42:30 +01:00
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2015-12-17 14:37:14 +01:00
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static bool have_guest_debug;
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2023-04-20 11:21:15 +02:00
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void kvm_arm_init_debug(KVMState *s)
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2015-12-17 14:37:14 +01:00
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{
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2023-04-20 11:21:15 +02:00
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have_guest_debug = kvm_check_extension(s,
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2015-12-17 14:37:14 +01:00
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KVM_CAP_SET_GUEST_DEBUG);
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2015-12-17 14:37:15 +01:00
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2023-04-20 11:21:15 +02:00
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max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS);
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2015-12-17 14:37:15 +01:00
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hw_watchpoints = g_array_sized_new(true, true,
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sizeof(HWWatchpoint), max_hw_wps);
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2023-04-20 11:21:15 +02:00
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max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS);
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2015-12-17 14:37:15 +01:00
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hw_breakpoints = g_array_sized_new(true, true,
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sizeof(HWBreakpoint), max_hw_bps);
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2015-12-17 14:37:14 +01:00
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return;
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}
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2023-08-07 17:57:00 +02:00
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int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
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2015-12-17 14:37:15 +01:00
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{
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switch (type) {
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case GDB_BREAKPOINT_HW:
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return insert_hw_breakpoint(addr);
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break;
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case GDB_WATCHPOINT_READ:
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case GDB_WATCHPOINT_WRITE:
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case GDB_WATCHPOINT_ACCESS:
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return insert_hw_watchpoint(addr, len, type);
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default:
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return -ENOSYS;
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}
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}
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2023-08-07 17:57:00 +02:00
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int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
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2015-12-17 14:37:15 +01:00
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{
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switch (type) {
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case GDB_BREAKPOINT_HW:
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return delete_hw_breakpoint(addr);
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case GDB_WATCHPOINT_READ:
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case GDB_WATCHPOINT_WRITE:
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case GDB_WATCHPOINT_ACCESS:
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return delete_hw_watchpoint(addr, len, type);
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default:
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return -ENOSYS;
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}
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}
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void kvm_arch_remove_all_hw_breakpoints(void)
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{
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if (cur_hw_wps > 0) {
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g_array_remove_range(hw_watchpoints, 0, cur_hw_wps);
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}
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if (cur_hw_bps > 0) {
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g_array_remove_range(hw_breakpoints, 0, cur_hw_bps);
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}
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}
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void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
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{
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int i;
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memset(ptr, 0, sizeof(struct kvm_guest_debug_arch));
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for (i = 0; i < max_hw_wps; i++) {
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HWWatchpoint *wp = get_hw_wp(i);
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ptr->dbg_wcr[i] = wp->wcr;
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ptr->dbg_wvr[i] = wp->wvr;
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}
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for (i = 0; i < max_hw_bps; i++) {
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HWBreakpoint *bp = get_hw_bp(i);
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ptr->dbg_bcr[i] = bp->bcr;
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ptr->dbg_bvr[i] = bp->bvr;
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}
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}
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bool kvm_arm_hw_debug_active(CPUState *cs)
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{
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return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
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}
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2020-10-01 08:17:18 +02:00
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static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr,
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const char *name)
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2016-06-14 16:59:12 +02:00
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{
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int err;
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2017-09-04 16:21:54 +02:00
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err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
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if (err != 0) {
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2020-10-01 08:17:18 +02:00
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error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err));
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2017-09-04 16:21:54 +02:00
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return false;
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2016-06-14 16:59:12 +02:00
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}
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2017-09-04 16:21:54 +02:00
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err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);
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2017-09-04 16:21:54 +02:00
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if (err != 0) {
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2020-10-01 08:17:18 +02:00
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error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err));
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2017-09-04 16:21:54 +02:00
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return false;
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2016-06-14 16:59:12 +02:00
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}
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2017-09-04 16:21:54 +02:00
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return true;
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}
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2016-06-14 16:59:12 +02:00
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2017-09-04 16:21:54 +02:00
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void kvm_arm_pmu_init(CPUState *cs)
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2017-09-04 16:21:54 +02:00
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{
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struct kvm_device_attr attr = {
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.group = KVM_ARM_VCPU_PMU_V3_CTRL,
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.attr = KVM_ARM_VCPU_PMU_V3_INIT,
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};
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2017-09-04 16:21:54 +02:00
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if (!ARM_CPU(cs)->has_pmu) {
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return;
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}
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2020-10-01 08:17:18 +02:00
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if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
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2017-09-04 16:21:54 +02:00
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error_report("failed to init PMU");
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abort();
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}
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2017-09-04 16:21:54 +02:00
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}
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2017-09-04 16:21:54 +02:00
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void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
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2017-09-04 16:21:54 +02:00
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{
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struct kvm_device_attr attr = {
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.group = KVM_ARM_VCPU_PMU_V3_CTRL,
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.addr = (intptr_t)&irq,
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.attr = KVM_ARM_VCPU_PMU_V3_IRQ,
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};
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2016-06-14 16:59:12 +02:00
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2017-09-04 16:21:54 +02:00
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if (!ARM_CPU(cs)->has_pmu) {
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return;
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}
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2020-10-01 08:17:18 +02:00
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if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
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2017-09-04 16:21:54 +02:00
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error_report("failed to set irq for PMU");
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abort();
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}
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2016-06-14 16:59:12 +02:00
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}
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2015-12-17 14:37:15 +01:00
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2020-10-01 08:17:18 +02:00
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void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
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{
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struct kvm_device_attr attr = {
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.group = KVM_ARM_VCPU_PVTIME_CTRL,
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.attr = KVM_ARM_VCPU_PVTIME_IPA,
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.addr = (uint64_t)&ipa,
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};
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if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) {
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return;
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}
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if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) {
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error_report("failed to init PVTIME IPA");
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abort();
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}
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}
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2018-11-19 16:29:07 +01:00
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static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
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{
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uint64_t ret;
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struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
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int err;
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assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
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err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
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if (err < 0) {
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return -1;
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}
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*pret = ret;
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return 0;
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}
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static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
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{
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struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
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assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
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return ioctl(fd, KVM_GET_ONE_REG, &idreg);
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}
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2022-01-07 16:01:54 +01:00
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static bool kvm_arm_pauth_supported(void)
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{
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return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) &&
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kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
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}
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2018-03-09 18:09:44 +01:00
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bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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2013-12-17 20:42:30 +01:00
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{
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/* Identify the feature bits corresponding to the host CPU, and
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* fill out the ARMHostCPUClass fields accordingly. To do this
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* we have to create a scratch VM, create a single CPU inside it,
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* and then query that CPU for the relevant ID registers.
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*/
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int fdarray[3];
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2019-10-31 15:27:34 +01:00
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bool sve_supported;
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target/arm: Make number of counters in PMCR follow the CPU
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
specify the PMCR reset value (obtained from the appropriate TRM), and
use the 'N' field of that value to define the number of counters
provided.
This means that we now supply 6 counters instead of 4 for:
Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72,
Cortex-A76, Neoverse-N1, '-cpu max'
This CPU goes from 4 to 8 counters:
A64FX
These CPUs remain with 4 counters:
Cortex-A7, Cortex-A8
This CPU goes down from 4 to 3 counters:
Cortex-R5
Note that because we now use the PMCR reset value of the specific
implementation, we no longer set the LC bit out of reset. This has
an UNKNOWN value out of reset for all cores with any AArch32 support,
so guest software should be setting it anyway if it wants it.
This change was originally landed in commit f7fb73b8cdd3f7 (during
the 6.0 release cycle) but was then reverted by commit
21c2dd77a6aa517 before that release because it did not work with KVM.
This version fixes that by creating the scratch vCPU in
kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature
if KVM supports it, and then only asking KVM for the PMCR_EL0 value
if the vCPU has a PMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Added the correct value for a64fx]
Message-id: 20220513122852.4063586-1-peter.maydell@linaro.org
2022-05-13 14:28:52 +02:00
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bool pmu_supported = false;
|
2013-12-17 20:42:30 +01:00
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uint64_t features = 0;
|
2018-11-19 16:29:07 +01:00
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int err;
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|
2013-12-17 20:42:30 +01:00
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|
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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* we know these will only support creating one kind of guest CPU,
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* which is its preferred CPU type. Fortunately these old kernels
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* support only a very limited number of CPUs.
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*/
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static const uint32_t cpus_to_try[] = {
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KVM_ARM_TARGET_AEM_V8,
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KVM_ARM_TARGET_FOUNDATION_V8,
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KVM_ARM_TARGET_CORTEX_A57,
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|
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QEMU_KVM_ARM_TARGET_NONE
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};
|
2019-10-31 15:27:32 +01:00
|
|
|
/*
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|
|
* target = -1 informs kvm_arm_create_scratch_host_vcpu()
|
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|
|
* to use the preferred target
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*/
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|
struct kvm_vcpu_init init = { .target = -1, };
|
2013-12-17 20:42:30 +01:00
|
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2022-01-07 16:01:54 +01:00
|
|
|
/*
|
2022-08-01 17:21:18 +02:00
|
|
|
* Ask for SVE if supported, so that we can query ID_AA64ZFR0,
|
|
|
|
* which is otherwise RAZ.
|
|
|
|
*/
|
|
|
|
sve_supported = kvm_arm_sve_supported();
|
|
|
|
if (sve_supported) {
|
|
|
|
init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ask for Pointer Authentication if supported, so that we get
|
|
|
|
* the unsanitized field values for AA64ISAR1_EL1.
|
2022-01-07 16:01:54 +01:00
|
|
|
*/
|
|
|
|
if (kvm_arm_pauth_supported()) {
|
|
|
|
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
|
|
|
|
1 << KVM_ARM_VCPU_PTRAUTH_GENERIC);
|
|
|
|
}
|
|
|
|
|
target/arm: Make number of counters in PMCR follow the CPU
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
specify the PMCR reset value (obtained from the appropriate TRM), and
use the 'N' field of that value to define the number of counters
provided.
This means that we now supply 6 counters instead of 4 for:
Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72,
Cortex-A76, Neoverse-N1, '-cpu max'
This CPU goes from 4 to 8 counters:
A64FX
These CPUs remain with 4 counters:
Cortex-A7, Cortex-A8
This CPU goes down from 4 to 3 counters:
Cortex-R5
Note that because we now use the PMCR reset value of the specific
implementation, we no longer set the LC bit out of reset. This has
an UNKNOWN value out of reset for all cores with any AArch32 support,
so guest software should be setting it anyway if it wants it.
This change was originally landed in commit f7fb73b8cdd3f7 (during
the 6.0 release cycle) but was then reverted by commit
21c2dd77a6aa517 before that release because it did not work with KVM.
This version fixes that by creating the scratch vCPU in
kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature
if KVM supports it, and then only asking KVM for the PMCR_EL0 value
if the vCPU has a PMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Added the correct value for a64fx]
Message-id: 20220513122852.4063586-1-peter.maydell@linaro.org
2022-05-13 14:28:52 +02:00
|
|
|
if (kvm_arm_pmu_supported()) {
|
|
|
|
init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
|
|
|
|
pmu_supported = true;
|
|
|
|
}
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-03-09 18:09:44 +01:00
|
|
|
ahcf->target = init.target;
|
|
|
|
ahcf->dtb_compatible = "arm,arm-v8";
|
2013-12-17 20:42:30 +01:00
|
|
|
|
2018-11-19 16:29:07 +01:00
|
|
|
err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 4, 0));
|
|
|
|
if (unlikely(err < 0)) {
|
|
|
|
/*
|
|
|
|
* Before v4.15, the kernel only exposed a limited number of system
|
|
|
|
* registers, not including any of the interesting AArch64 ID regs.
|
|
|
|
* For the most part we could leave these fields as zero with minimal
|
|
|
|
* effect, since this does not affect the values seen by the guest.
|
|
|
|
*
|
|
|
|
* However, it could cause problems down the line for QEMU,
|
|
|
|
* so provide a minimal v8.0 default.
|
|
|
|
*
|
|
|
|
* ??? Could read MIDR and use knowledge from cpu64.c.
|
|
|
|
* ??? Could map a page of memory into our temp guest and
|
|
|
|
* run the tiniest of hand-crafted kernels to extract
|
|
|
|
* the values seen by the guest.
|
|
|
|
* ??? Either of these sounds like too much effort just
|
|
|
|
* to work around running a modern host kernel.
|
|
|
|
*/
|
|
|
|
ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
|
|
|
|
err = 0;
|
|
|
|
} else {
|
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 4, 1));
|
2022-06-08 20:38:59 +02:00
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 4, 5));
|
2020-02-14 18:51:07 +01:00
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 5, 0));
|
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 5, 1));
|
2018-11-19 16:29:07 +01:00
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 6, 0));
|
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 6, 1));
|
2023-08-30 01:23:25 +02:00
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 6, 2));
|
2018-12-13 15:40:56 +01:00
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 7, 0));
|
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 7, 1));
|
2020-02-08 13:58:13 +01:00
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 7, 2));
|
2018-11-19 16:29:07 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that if AArch32 support is not present in the host,
|
|
|
|
* the AArch32 sysregs are present to be read, but will
|
|
|
|
* return UNKNOWN values. This is neither better nor worse
|
|
|
|
* than skipping the reads and leaving 0, as we must avoid
|
|
|
|
* considering the values in every case.
|
|
|
|
*/
|
2020-09-10 19:38:52 +02:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 1, 0));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 1, 1));
|
2020-02-14 18:51:07 +01:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 1, 2));
|
2020-02-14 18:51:13 +01:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 1, 4));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 1, 5));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 1, 6));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 1, 7));
|
2018-11-19 16:29:07 +01:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 0));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 1));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 2));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 3));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 4));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 5));
|
2020-02-14 18:51:13 +01:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 6));
|
2018-11-19 16:29:07 +01:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 2, 7));
|
|
|
|
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 3, 0));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 3, 1));
|
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 3, 2));
|
2022-08-19 13:00:48 +02:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 3, 4));
|
2022-08-19 13:00:50 +02:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 3, 5));
|
2022-08-19 13:00:49 +02:00
|
|
|
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 3, 6));
|
2020-02-14 18:51:07 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* DBGDIDR is a bit complicated because the kernel doesn't
|
|
|
|
* provide an accessor for it in 64-bit mode, which is what this
|
|
|
|
* scratch VM is in, and there's no architected "64-bit sysreg
|
|
|
|
* which reads the same as the 32-bit register" the way there is
|
|
|
|
* for other ID registers. Instead we synthesize a value from the
|
|
|
|
* AArch64 ID_AA64DFR0, the same way the kernel code in
|
|
|
|
* arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
|
|
|
|
* We only do this if the CPU supports AArch32 at EL1.
|
|
|
|
*/
|
|
|
|
if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
|
|
|
|
int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
|
|
|
|
int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
|
|
|
|
int ctx_cmps =
|
|
|
|
FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
|
|
|
|
int version = 6; /* ARMv8 debug architecture */
|
|
|
|
bool has_el3 =
|
|
|
|
!!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
|
|
|
|
uint32_t dbgdidr = 0;
|
|
|
|
|
|
|
|
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
|
|
|
|
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps);
|
|
|
|
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps);
|
|
|
|
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version);
|
|
|
|
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3);
|
|
|
|
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3);
|
|
|
|
dbgdidr |= (1 << 15); /* RES1 bit */
|
|
|
|
ahcf->isar.dbgdidr = dbgdidr;
|
|
|
|
}
|
target/arm: Make number of counters in PMCR follow the CPU
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
specify the PMCR reset value (obtained from the appropriate TRM), and
use the 'N' field of that value to define the number of counters
provided.
This means that we now supply 6 counters instead of 4 for:
Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72,
Cortex-A76, Neoverse-N1, '-cpu max'
This CPU goes from 4 to 8 counters:
A64FX
These CPUs remain with 4 counters:
Cortex-A7, Cortex-A8
This CPU goes down from 4 to 3 counters:
Cortex-R5
Note that because we now use the PMCR reset value of the specific
implementation, we no longer set the LC bit out of reset. This has
an UNKNOWN value out of reset for all cores with any AArch32 support,
so guest software should be setting it anyway if it wants it.
This change was originally landed in commit f7fb73b8cdd3f7 (during
the 6.0 release cycle) but was then reverted by commit
21c2dd77a6aa517 before that release because it did not work with KVM.
This version fixes that by creating the scratch vCPU in
kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature
if KVM supports it, and then only asking KVM for the PMCR_EL0 value
if the vCPU has a PMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Added the correct value for a64fx]
Message-id: 20220513122852.4063586-1-peter.maydell@linaro.org
2022-05-13 14:28:52 +02:00
|
|
|
|
|
|
|
if (pmu_supported) {
|
|
|
|
/* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */
|
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
|
|
|
|
ARM64_SYS_REG(3, 3, 9, 12, 0));
|
|
|
|
}
|
2018-11-19 16:29:07 +01:00
|
|
|
|
2022-08-01 17:21:18 +02:00
|
|
|
if (sve_supported) {
|
|
|
|
/*
|
|
|
|
* There is a range of kernels between kernel commit 73433762fcae
|
|
|
|
* and f81cb2c3ad41 which have a bug where the kernel doesn't
|
|
|
|
* expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
|
|
|
|
* enabled SVE support, which resulted in an error rather than RAZ.
|
|
|
|
* So only read the register if we set KVM_ARM_VCPU_SVE above.
|
|
|
|
*/
|
|
|
|
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
|
|
|
|
ARM64_SYS_REG(3, 0, 0, 4, 4));
|
|
|
|
}
|
2021-05-25 03:02:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
kvm_arm_destroy_scratch_host_vcpu(fdarray);
|
|
|
|
|
|
|
|
if (err < 0) {
|
|
|
|
return false;
|
2019-10-31 15:27:34 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We can assume any KVM supporting CPU is at least a v8
|
2013-12-17 20:42:30 +01:00
|
|
|
* with VFPv4+Neon; this in turn implies most of the other
|
|
|
|
* feature bits.
|
|
|
|
*/
|
2020-05-04 19:24:44 +02:00
|
|
|
features |= 1ULL << ARM_FEATURE_V8;
|
|
|
|
features |= 1ULL << ARM_FEATURE_NEON;
|
|
|
|
features |= 1ULL << ARM_FEATURE_AARCH64;
|
|
|
|
features |= 1ULL << ARM_FEATURE_PMU;
|
|
|
|
features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
|
2013-12-17 20:42:30 +01:00
|
|
|
|
2018-03-09 18:09:44 +01:00
|
|
|
ahcf->features = features;
|
2013-12-17 20:42:30 +01:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2020-10-01 08:17:18 +02:00
|
|
|
void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
|
|
|
|
{
|
|
|
|
bool has_steal_time = kvm_arm_steal_time_supported();
|
|
|
|
|
|
|
|
if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) {
|
|
|
|
if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
|
|
|
|
cpu->kvm_steal_time = ON_OFF_AUTO_OFF;
|
|
|
|
} else {
|
|
|
|
cpu->kvm_steal_time = ON_OFF_AUTO_ON;
|
|
|
|
}
|
|
|
|
} else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) {
|
|
|
|
if (!has_steal_time) {
|
|
|
|
error_setg(errp, "'kvm-steal-time' cannot be enabled "
|
|
|
|
"on this host");
|
|
|
|
return;
|
|
|
|
} else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
|
|
|
|
/*
|
|
|
|
* DEN0057A chapter 2 says "This specification only covers
|
|
|
|
* systems in which the Execution state of the hypervisor
|
|
|
|
* as well as EL1 of virtual machines is AArch64.". And,
|
|
|
|
* to ensure that, the smc/hvc calls are only specified as
|
|
|
|
* smc64/hvc64.
|
|
|
|
*/
|
|
|
|
error_setg(errp, "'kvm-steal-time' cannot be enabled "
|
|
|
|
"for AArch32 guests");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
target/arm: Check supported KVM features globally (not per vCPU)
Since commit d70c996df23f, when enabling the PMU we get:
$ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
Segmentation fault (core dumped)
Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
2588 ret = ioctl(s->fd, type, arg);
(gdb) bt
#0 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
#1 0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
#2 0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
#3 0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
#4 0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
#5 0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
#6 0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
#7 0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
#8 0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
#9 0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
...
#15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
#16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
#17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
#18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
#19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
#20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
#21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48
This is because in frame #2, cpu->kvm_state is still NULL
(the vCPU is not yet realized).
KVM has a hard requirement of all cores supporting the same
feature set. We only need to check if the accelerator supports
a feature, not each vCPU individually.
Fix by removing the 'CPUState *cpu' argument from the
kvm_arm_<FEATURE>_supported() functions.
Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
Reported-by: Haibo Xu <haibo.xu@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 11:06:22 +02:00
|
|
|
bool kvm_arm_aarch32_supported(void)
|
2019-08-02 14:25:26 +02:00
|
|
|
{
|
target/arm: Check supported KVM features globally (not per vCPU)
Since commit d70c996df23f, when enabling the PMU we get:
$ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
Segmentation fault (core dumped)
Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
2588 ret = ioctl(s->fd, type, arg);
(gdb) bt
#0 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
#1 0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
#2 0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
#3 0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
#4 0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
#5 0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
#6 0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
#7 0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
#8 0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
#9 0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
...
#15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
#16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
#17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
#18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
#19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
#20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
#21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48
This is because in frame #2, cpu->kvm_state is still NULL
(the vCPU is not yet realized).
KVM has a hard requirement of all cores supporting the same
feature set. We only need to check if the accelerator supports
a feature, not each vCPU individually.
Fix by removing the 'CPUState *cpu' argument from the
kvm_arm_<FEATURE>_supported() functions.
Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
Reported-by: Haibo Xu <haibo.xu@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 11:06:22 +02:00
|
|
|
return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
|
2019-08-02 14:25:26 +02:00
|
|
|
}
|
|
|
|
|
target/arm: Check supported KVM features globally (not per vCPU)
Since commit d70c996df23f, when enabling the PMU we get:
$ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
Segmentation fault (core dumped)
Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
2588 ret = ioctl(s->fd, type, arg);
(gdb) bt
#0 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
#1 0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
#2 0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
#3 0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
#4 0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
#5 0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
#6 0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
#7 0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
#8 0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
#9 0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
...
#15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
#16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
#17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
#18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
#19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
#20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
#21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48
This is because in frame #2, cpu->kvm_state is still NULL
(the vCPU is not yet realized).
KVM has a hard requirement of all cores supporting the same
feature set. We only need to check if the accelerator supports
a feature, not each vCPU individually.
Fix by removing the 'CPUState *cpu' argument from the
kvm_arm_<FEATURE>_supported() functions.
Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
Reported-by: Haibo Xu <haibo.xu@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 11:06:22 +02:00
|
|
|
bool kvm_arm_sve_supported(void)
|
2019-10-31 15:27:31 +01:00
|
|
|
{
|
target/arm: Check supported KVM features globally (not per vCPU)
Since commit d70c996df23f, when enabling the PMU we get:
$ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
Segmentation fault (core dumped)
Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
2588 ret = ioctl(s->fd, type, arg);
(gdb) bt
#0 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
#1 0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
#2 0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
#3 0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
#4 0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
#5 0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
#6 0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
#7 0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
#8 0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
#9 0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
...
#15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
#16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
#17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
#18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
#19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
#20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
#21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48
This is because in frame #2, cpu->kvm_state is still NULL
(the vCPU is not yet realized).
KVM has a hard requirement of all cores supporting the same
feature set. We only need to check if the accelerator supports
a feature, not each vCPU individually.
Fix by removing the 'CPUState *cpu' argument from the
kvm_arm_<FEATURE>_supported() functions.
Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
Reported-by: Haibo Xu <haibo.xu@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 11:06:22 +02:00
|
|
|
return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
|
2019-10-31 15:27:31 +01:00
|
|
|
}
|
|
|
|
|
2020-10-01 08:17:18 +02:00
|
|
|
bool kvm_arm_steal_time_supported(void)
|
|
|
|
{
|
|
|
|
return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME);
|
|
|
|
}
|
|
|
|
|
2019-10-31 15:27:33 +01:00
|
|
|
QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
|
|
|
|
|
2022-06-08 20:38:57 +02:00
|
|
|
uint32_t kvm_arm_sve_get_vls(CPUState *cs)
|
2019-10-31 15:27:33 +01:00
|
|
|
{
|
|
|
|
/* Only call this function if kvm_arm_sve_supported() returns true. */
|
|
|
|
static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];
|
|
|
|
static bool probed;
|
|
|
|
uint32_t vq = 0;
|
2022-06-08 20:38:57 +02:00
|
|
|
int i;
|
2019-10-31 15:27:33 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* KVM ensures all host CPUs support the same set of vector lengths.
|
|
|
|
* So we only need to create the scratch VCPUs once and then cache
|
|
|
|
* the results.
|
|
|
|
*/
|
|
|
|
if (!probed) {
|
|
|
|
struct kvm_vcpu_init init = {
|
|
|
|
.target = -1,
|
|
|
|
.features[0] = (1 << KVM_ARM_VCPU_SVE),
|
|
|
|
};
|
|
|
|
struct kvm_one_reg reg = {
|
|
|
|
.id = KVM_REG_ARM64_SVE_VLS,
|
|
|
|
.addr = (uint64_t)&vls[0],
|
|
|
|
};
|
|
|
|
int fdarray[3], ret;
|
|
|
|
|
|
|
|
probed = true;
|
|
|
|
|
|
|
|
if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) {
|
|
|
|
error_report("failed to create scratch VCPU with SVE enabled");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®);
|
|
|
|
kvm_arm_destroy_scratch_host_vcpu(fdarray);
|
|
|
|
if (ret) {
|
|
|
|
error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
|
|
|
|
strerror(errno));
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {
|
|
|
|
if (vls[i]) {
|
|
|
|
vq = 64 - clz64(vls[i]) + i * 64;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (vq > ARM_MAX_VQ) {
|
|
|
|
warn_report("KVM supports vector lengths larger than "
|
|
|
|
"QEMU can enable");
|
2022-06-08 20:38:57 +02:00
|
|
|
vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ);
|
2019-10-31 15:27:33 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-08 20:38:57 +02:00
|
|
|
return vls[0];
|
2019-10-31 15:27:33 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_arm_sve_set_vls(CPUState *cs)
|
|
|
|
{
|
2022-06-08 20:38:57 +02:00
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
2022-06-20 19:51:56 +02:00
|
|
|
uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };
|
2019-10-31 15:27:33 +01:00
|
|
|
struct kvm_one_reg reg = {
|
|
|
|
.id = KVM_REG_ARM64_SVE_VLS,
|
|
|
|
.addr = (uint64_t)&vls[0],
|
|
|
|
};
|
|
|
|
|
|
|
|
assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
|
|
|
|
|
|
|
|
return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
}
|
|
|
|
|
2015-06-15 19:06:09 +02:00
|
|
|
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
int kvm_arch_init_vcpu(CPUState *cs)
|
|
|
|
{
|
|
|
|
int ret;
|
2015-06-15 19:06:09 +02:00
|
|
|
uint64_t mpidr;
|
2014-06-19 19:06:26 +02:00
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
2016-10-28 15:12:31 +02:00
|
|
|
CPUARMState *env = &cpu->env;
|
2022-02-24 14:46:54 +01:00
|
|
|
uint64_t psciver;
|
2013-12-17 20:42:30 +01:00
|
|
|
|
|
|
|
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
|
2015-02-13 06:46:08 +01:00
|
|
|
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
|
2019-10-31 15:27:33 +01:00
|
|
|
error_report("KVM is not supported for this guest CPU type");
|
2013-12-17 20:42:30 +01:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-01-30 17:02:06 +01:00
|
|
|
qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
|
|
|
|
|
2014-06-19 19:06:26 +02:00
|
|
|
/* Determine init features for this CPU */
|
|
|
|
memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
|
2020-08-26 07:55:28 +02:00
|
|
|
if (cs->start_powered_off) {
|
2014-06-19 19:06:26 +02:00
|
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
|
|
|
|
}
|
2014-06-19 19:06:26 +02:00
|
|
|
if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
|
2022-02-13 04:57:53 +01:00
|
|
|
cpu->psci_version = QEMU_PSCI_VERSION_0_2;
|
2014-06-19 19:06:26 +02:00
|
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
|
|
|
|
}
|
2015-02-13 06:46:08 +01:00
|
|
|
if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
|
|
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
|
|
|
|
}
|
2017-09-04 16:21:54 +02:00
|
|
|
if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
|
2019-10-31 15:27:31 +01:00
|
|
|
cpu->has_pmu = false;
|
2016-10-28 15:12:31 +02:00
|
|
|
}
|
|
|
|
if (cpu->has_pmu) {
|
2016-06-14 16:59:12 +02:00
|
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
|
2016-10-28 15:12:31 +02:00
|
|
|
} else {
|
2020-05-04 19:24:44 +02:00
|
|
|
env->features &= ~(1ULL << ARM_FEATURE_PMU);
|
2016-06-14 16:59:12 +02:00
|
|
|
}
|
2019-10-31 15:27:31 +01:00
|
|
|
if (cpu_isar_feature(aa64_sve, cpu)) {
|
target/arm: Check supported KVM features globally (not per vCPU)
Since commit d70c996df23f, when enabling the PMU we get:
$ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
Segmentation fault (core dumped)
Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
2588 ret = ioctl(s->fd, type, arg);
(gdb) bt
#0 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588
#1 0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916
#2 0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213
#3 0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111
#4 0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170
#5 0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328
#6 0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561
#7 0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
#8 0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218
#9 0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050
...
#15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512
#16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687
#17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702
#18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770
#19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138
#20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348
#21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48
This is because in frame #2, cpu->kvm_state is still NULL
(the vCPU is not yet realized).
KVM has a hard requirement of all cores supporting the same
feature set. We only need to check if the accelerator supports
a feature, not each vCPU individually.
Fix by removing the 'CPUState *cpu' argument from the
kvm_arm_<FEATURE>_supported() functions.
Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
Reported-by: Haibo Xu <haibo.xu@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23 11:06:22 +02:00
|
|
|
assert(kvm_arm_sve_supported());
|
2019-10-31 15:27:31 +01:00
|
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
|
|
|
|
}
|
2022-01-07 16:01:54 +01:00
|
|
|
if (cpu_isar_feature(aa64_pauth, cpu)) {
|
|
|
|
cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
|
|
|
|
1 << KVM_ARM_VCPU_PTRAUTH_GENERIC);
|
|
|
|
}
|
2014-06-19 19:06:26 +02:00
|
|
|
|
|
|
|
/* Do KVM_ARM_VCPU_INIT ioctl */
|
|
|
|
ret = kvm_arm_vcpu_init(cs);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
2013-12-17 20:42:30 +01:00
|
|
|
}
|
|
|
|
|
2019-10-31 15:27:31 +01:00
|
|
|
if (cpu_isar_feature(aa64_sve, cpu)) {
|
2019-10-31 15:27:33 +01:00
|
|
|
ret = kvm_arm_sve_set_vls(cs);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
2019-10-31 15:27:31 +01:00
|
|
|
ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-02-24 14:46:54 +01:00
|
|
|
/*
|
|
|
|
* KVM reports the exact PSCI version it is implementing via a
|
|
|
|
* special sysreg. If it is present, use its contents to determine
|
|
|
|
* what to report to the guest in the dtb (it is the PSCI version,
|
|
|
|
* in the same 15-bits major 16-bits minor format that PSCI_VERSION
|
|
|
|
* returns).
|
|
|
|
*/
|
|
|
|
if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) {
|
|
|
|
cpu->psci_version = psciver;
|
|
|
|
}
|
|
|
|
|
2015-06-15 19:06:09 +02:00
|
|
|
/*
|
|
|
|
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
|
|
|
|
* Currently KVM has its own idea about MPIDR assignment, so we
|
|
|
|
* override our defaults with what we get from KVM.
|
|
|
|
*/
|
|
|
|
ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
2015-09-07 11:39:31 +02:00
|
|
|
cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
|
2015-06-15 19:06:09 +02:00
|
|
|
|
2018-10-24 08:50:16 +02:00
|
|
|
/* Check whether user space can specify guest syndrome value */
|
|
|
|
kvm_arm_init_serror_injection(cs);
|
|
|
|
|
2014-12-11 13:07:53 +01:00
|
|
|
return kvm_arm_init_cpreg_list(cpu);
|
|
|
|
}
|
2013-12-17 20:42:30 +01:00
|
|
|
|
2019-06-19 18:21:32 +02:00
|
|
|
int kvm_arch_destroy_vcpu(CPUState *cs)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-12-11 13:07:53 +01:00
|
|
|
bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
|
|
|
|
{
|
|
|
|
/* Return true if the regidx is a register we should synchronize
|
2019-10-31 15:27:30 +01:00
|
|
|
* via the cpreg_tuples array (ie is not a core or sve reg that
|
|
|
|
* we sync by hand in kvm_arch_get/put_registers())
|
2014-12-11 13:07:53 +01:00
|
|
|
*/
|
|
|
|
switch (regidx & KVM_REG_ARM_COPROC_MASK) {
|
|
|
|
case KVM_REG_ARM_CORE:
|
2019-10-31 15:27:30 +01:00
|
|
|
case KVM_REG_ARM64_SVE:
|
2014-12-11 13:07:53 +01:00
|
|
|
return false;
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
2013-12-17 20:42:30 +01:00
|
|
|
}
|
|
|
|
|
2015-07-21 12:18:45 +02:00
|
|
|
typedef struct CPRegStateLevel {
|
|
|
|
uint64_t regidx;
|
|
|
|
int level;
|
|
|
|
} CPRegStateLevel;
|
|
|
|
|
|
|
|
/* All system registers not listed in the following table are assumed to be
|
|
|
|
* of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
|
|
|
|
* often, you must add it to this table with a state of either
|
|
|
|
* KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
|
|
|
|
*/
|
|
|
|
static const CPRegStateLevel non_runtime_cpregs[] = {
|
|
|
|
{ KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
|
2023-08-31 21:00:52 +02:00
|
|
|
{ KVM_REG_ARM_PTIMER_CNT, KVM_PUT_FULL_STATE },
|
2015-07-21 12:18:45 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
int kvm_arm_cpreg_level(uint64_t regidx)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
|
|
|
|
const CPRegStateLevel *l = &non_runtime_cpregs[i];
|
|
|
|
if (l->regidx == regidx) {
|
|
|
|
return l->level;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return KVM_PUT_RUNTIME_STATE;
|
|
|
|
}
|
|
|
|
|
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
External Abort(SEA). Then host kernel gets an APEI notification and calls
memory_failure() to unmapped the affected page in stage 2, finally
returns to guest.
Guest continues to access the PG_hwpoison page, it will trap to KVM as
stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
Qemu, Qemu records this error address into guest APEI GHES memory and
notifes guest using Synchronous-External-Abort(SEA).
In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function
in which we can setup the type of exception and the syndrome information.
When switching to guest, the target vcpu will jump to the synchronous
external abort vector table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the
ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
not valid and hold an UNKNOWN value. These values will be set to KVM
register structures through KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20200512030609.19593-10-gengdongjiu@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-12 05:06:08 +02:00
|
|
|
/* Callers must hold the iothread mutex lock */
|
|
|
|
static void kvm_inject_arm_sea(CPUState *c)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(c);
|
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
uint32_t esr;
|
|
|
|
bool same_el;
|
|
|
|
|
|
|
|
c->exception_index = EXCP_DATA_ABORT;
|
|
|
|
env->exception.target_el = 1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the DFSC to synchronous external abort and set FnV to not valid,
|
|
|
|
* this will tell guest the FAR_ELx is UNKNOWN for this abort.
|
|
|
|
*/
|
|
|
|
same_el = arm_current_el(env) == env->exception.target_el;
|
|
|
|
esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10);
|
|
|
|
|
|
|
|
env->exception.syndrome = esr;
|
|
|
|
|
2021-02-04 17:39:16 +01:00
|
|
|
arm_cpu_do_interrupt(c);
|
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
External Abort(SEA). Then host kernel gets an APEI notification and calls
memory_failure() to unmapped the affected page in stage 2, finally
returns to guest.
Guest continues to access the PG_hwpoison page, it will trap to KVM as
stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
Qemu, Qemu records this error address into guest APEI GHES memory and
notifes guest using Synchronous-External-Abort(SEA).
In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function
in which we can setup the type of exception and the syndrome information.
When switching to guest, the target vcpu will jump to the synchronous
external abort vector table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the
ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
not valid and hold an UNKNOWN value. These values will be set to KVM
register structures through KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20200512030609.19593-10-gengdongjiu@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-12 05:06:08 +02:00
|
|
|
}
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
|
|
|
|
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
|
|
|
|
|
2015-04-01 18:57:30 +02:00
|
|
|
#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
|
|
|
|
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
|
|
|
|
|
|
|
|
#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
|
|
|
|
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
|
|
|
|
|
2019-08-02 14:25:35 +02:00
|
|
|
static int kvm_arch_put_fpsimd(CPUState *cs)
|
2013-12-17 20:42:30 +01:00
|
|
|
{
|
2019-10-31 15:27:30 +01:00
|
|
|
CPUARMState *env = &ARM_CPU(cs)->env;
|
2013-12-17 20:42:30 +01:00
|
|
|
struct kvm_one_reg reg;
|
2019-08-02 14:25:35 +02:00
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
uint64_t *q = aa64_vfp_qreg(env, i);
|
2022-03-23 16:57:17 +01:00
|
|
|
#if HOST_BIG_ENDIAN
|
2019-08-02 14:25:35 +02:00
|
|
|
uint64_t fp_val[2] = { q[1], q[0] };
|
|
|
|
reg.addr = (uintptr_t)fp_val;
|
|
|
|
#else
|
|
|
|
reg.addr = (uintptr_t)q;
|
|
|
|
#endif
|
|
|
|
reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-31 15:27:30 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
|
|
|
|
* and PREGS and the FFR have a slice size of 256 bits. However we simply hard
|
|
|
|
* code the slice index to zero for now as it's unlikely we'll need more than
|
|
|
|
* one slice for quite some time.
|
|
|
|
*/
|
|
|
|
static int kvm_arch_put_sve(CPUState *cs)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
uint64_t tmp[ARM_MAX_VQ * 2];
|
|
|
|
uint64_t *r;
|
|
|
|
struct kvm_one_reg reg;
|
|
|
|
int n, ret;
|
|
|
|
|
|
|
|
for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
|
|
|
|
r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
|
|
|
|
reg.addr = (uintptr_t)r;
|
|
|
|
reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
|
|
|
|
r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
|
|
|
|
DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
|
|
|
|
reg.addr = (uintptr_t)r;
|
|
|
|
reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
|
|
|
|
DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
|
|
|
|
reg.addr = (uintptr_t)r;
|
|
|
|
reg.id = KVM_REG_ARM64_SVE_FFR(0);
|
2019-08-02 14:25:35 +02:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int kvm_arch_put_registers(CPUState *cs, int level)
|
|
|
|
{
|
|
|
|
struct kvm_one_reg reg;
|
2013-12-17 20:42:30 +01:00
|
|
|
uint64_t val;
|
2019-10-31 15:27:30 +01:00
|
|
|
uint32_t fpr;
|
2019-08-02 14:25:35 +02:00
|
|
|
int i, ret;
|
2015-04-01 18:57:30 +02:00
|
|
|
unsigned int el;
|
2013-12-17 20:42:30 +01:00
|
|
|
|
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
|
2015-02-13 06:46:08 +01:00
|
|
|
/* If we are in AArch32 mode then we need to copy the AArch32 regs to the
|
|
|
|
* AArch64 registers before pushing them out to 64-bit KVM.
|
|
|
|
*/
|
|
|
|
if (!is_a64(env)) {
|
|
|
|
aarch64_sync_32_to_64(env);
|
|
|
|
}
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
for (i = 0; i < 31; i++) {
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.regs[i]);
|
|
|
|
reg.addr = (uintptr_t) &env->xregs[i];
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-15 20:18:43 +02:00
|
|
|
/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
|
|
|
|
* QEMU side we keep the current SP in xregs[31] as well.
|
|
|
|
*/
|
2014-08-04 15:41:54 +02:00
|
|
|
aarch64_save_sp(env, 1);
|
2014-04-15 20:18:43 +02:00
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
reg.id = AARCH64_CORE_REG(regs.sp);
|
2014-04-15 20:18:43 +02:00
|
|
|
reg.addr = (uintptr_t) &env->sp_el[0];
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.id = AARCH64_CORE_REG(sp_el1);
|
|
|
|
reg.addr = (uintptr_t) &env->sp_el[1];
|
2013-12-17 20:42:30 +01:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
|
2015-02-13 06:46:08 +01:00
|
|
|
if (is_a64(env)) {
|
|
|
|
val = pstate_read(env);
|
|
|
|
} else {
|
|
|
|
val = cpsr_read(env);
|
|
|
|
}
|
2013-12-17 20:42:30 +01:00
|
|
|
reg.id = AARCH64_CORE_REG(regs.pstate);
|
|
|
|
reg.addr = (uintptr_t) &val;
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.pc);
|
|
|
|
reg.addr = (uintptr_t) &env->pc;
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-04-15 20:18:42 +02:00
|
|
|
reg.id = AARCH64_CORE_REG(elr_el1);
|
2014-05-27 18:09:51 +02:00
|
|
|
reg.addr = (uintptr_t) &env->elr_el[1];
|
2014-04-15 20:18:42 +02:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-04-01 18:57:30 +02:00
|
|
|
/* Saved Program State Registers
|
|
|
|
*
|
|
|
|
* Before we restore from the banked_spsr[] array we need to
|
|
|
|
* ensure that any modifications to env->spsr are correctly
|
|
|
|
* reflected in the banks.
|
|
|
|
*/
|
|
|
|
el = arm_current_el(env);
|
|
|
|
if (el > 0 && !is_a64(env)) {
|
|
|
|
i = bank_number(env->uncached_cpsr & CPSR_M);
|
|
|
|
env->banked_spsr[i] = env->spsr;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* KVM 0-4 map to QEMU banks 1-5 */
|
2014-04-15 20:18:43 +02:00
|
|
|
for (i = 0; i < KVM_NR_SPSR; i++) {
|
|
|
|
reg.id = AARCH64_CORE_REG(spsr[i]);
|
2015-04-01 18:57:30 +02:00
|
|
|
reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
|
2014-04-15 20:18:43 +02:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-31 15:27:30 +01:00
|
|
|
if (cpu_isar_feature(aa64_sve, cpu)) {
|
|
|
|
ret = kvm_arch_put_sve(cs);
|
|
|
|
} else {
|
|
|
|
ret = kvm_arch_put_fpsimd(cs);
|
|
|
|
}
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.addr = (uintptr_t)(&fpr);
|
|
|
|
fpr = vfp_get_fpsr(env);
|
|
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.addr = (uintptr_t)(&fpr);
|
|
|
|
fpr = vfp_get_fpcr(env);
|
|
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
2019-08-02 14:25:35 +02:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
write_cpustate_to_list(cpu, true);
|
|
|
|
|
|
|
|
if (!write_list_to_kvmstate(cpu, level)) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-03-12 01:34:00 +01:00
|
|
|
/*
|
|
|
|
* Setting VCPU events should be triggered after syncing the registers
|
|
|
|
* to avoid overwriting potential changes made by KVM upon calling
|
|
|
|
* KVM_SET_VCPU_EVENTS ioctl
|
|
|
|
*/
|
|
|
|
ret = kvm_put_vcpu_events(cpu);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-08-02 14:25:35 +02:00
|
|
|
kvm_arm_sync_mpstate_to_kvm(cpu);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_arch_get_fpsimd(CPUState *cs)
|
|
|
|
{
|
2019-10-31 15:27:30 +01:00
|
|
|
CPUARMState *env = &ARM_CPU(cs)->env;
|
2019-08-02 14:25:35 +02:00
|
|
|
struct kvm_one_reg reg;
|
|
|
|
int i, ret;
|
|
|
|
|
2015-04-01 18:57:30 +02:00
|
|
|
for (i = 0; i < 32; i++) {
|
2018-01-25 12:45:29 +01:00
|
|
|
uint64_t *q = aa64_vfp_qreg(env, i);
|
2015-04-01 18:57:30 +02:00
|
|
|
reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
|
2019-08-02 14:25:35 +02:00
|
|
|
reg.addr = (uintptr_t)q;
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
2015-04-01 18:57:30 +02:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
2019-08-02 14:25:35 +02:00
|
|
|
} else {
|
2022-03-23 16:57:17 +01:00
|
|
|
#if HOST_BIG_ENDIAN
|
2019-08-02 14:25:35 +02:00
|
|
|
uint64_t t;
|
|
|
|
t = q[0], q[0] = q[1], q[1] = t;
|
|
|
|
#endif
|
2015-04-01 18:57:30 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-31 15:27:30 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
|
|
|
|
* and PREGS and the FFR have a slice size of 256 bits. However we simply hard
|
|
|
|
* code the slice index to zero for now as it's unlikely we'll need more than
|
|
|
|
* one slice for quite some time.
|
|
|
|
*/
|
|
|
|
static int kvm_arch_get_sve(CPUState *cs)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
struct kvm_one_reg reg;
|
|
|
|
uint64_t *r;
|
|
|
|
int n, ret;
|
|
|
|
|
|
|
|
for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
|
|
|
|
r = &env->vfp.zregs[n].d[0];
|
|
|
|
reg.addr = (uintptr_t)r;
|
|
|
|
reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
sve_bswap64(r, r, cpu->sve_max_vq * 2);
|
2015-04-01 18:57:30 +02:00
|
|
|
}
|
|
|
|
|
2019-10-31 15:27:30 +01:00
|
|
|
for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
|
|
|
|
r = &env->vfp.pregs[n].p[0];
|
|
|
|
reg.addr = (uintptr_t)r;
|
|
|
|
reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
|
|
|
|
}
|
|
|
|
|
|
|
|
r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
|
|
|
|
reg.addr = (uintptr_t)r;
|
|
|
|
reg.id = KVM_REG_ARM64_SVE_FFR(0);
|
2019-08-02 14:25:35 +02:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
2018-10-24 08:50:16 +02:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
2019-10-31 15:27:30 +01:00
|
|
|
sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
|
2018-10-24 08:50:16 +02:00
|
|
|
|
2019-08-02 14:25:35 +02:00
|
|
|
return 0;
|
2013-12-17 20:42:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
int kvm_arch_get_registers(CPUState *cs)
|
|
|
|
{
|
|
|
|
struct kvm_one_reg reg;
|
|
|
|
uint64_t val;
|
2015-04-01 18:57:30 +02:00
|
|
|
unsigned int el;
|
2019-10-31 15:27:30 +01:00
|
|
|
uint32_t fpr;
|
2019-08-02 14:25:35 +02:00
|
|
|
int i, ret;
|
2013-12-17 20:42:30 +01:00
|
|
|
|
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
|
|
|
|
for (i = 0; i < 31; i++) {
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.regs[i]);
|
|
|
|
reg.addr = (uintptr_t) &env->xregs[i];
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.sp);
|
2014-04-15 20:18:43 +02:00
|
|
|
reg.addr = (uintptr_t) &env->sp_el[0];
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.id = AARCH64_CORE_REG(sp_el1);
|
|
|
|
reg.addr = (uintptr_t) &env->sp_el[1];
|
2013-12-17 20:42:30 +01:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.pstate);
|
|
|
|
reg.addr = (uintptr_t) &val;
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
2015-02-13 06:46:08 +01:00
|
|
|
|
|
|
|
env->aarch64 = ((val & PSTATE_nRW) == 0);
|
|
|
|
if (is_a64(env)) {
|
|
|
|
pstate_write(env, val);
|
|
|
|
} else {
|
2016-02-23 16:36:43 +01:00
|
|
|
cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
|
2015-02-13 06:46:08 +01:00
|
|
|
}
|
2013-12-17 20:42:30 +01:00
|
|
|
|
2014-04-15 20:18:43 +02:00
|
|
|
/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
|
|
|
|
* QEMU side we keep the current SP in xregs[31] as well.
|
|
|
|
*/
|
2014-08-04 15:41:54 +02:00
|
|
|
aarch64_restore_sp(env, 1);
|
2014-04-15 20:18:43 +02:00
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
reg.id = AARCH64_CORE_REG(regs.pc);
|
|
|
|
reg.addr = (uintptr_t) &env->pc;
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-02-13 06:46:08 +01:00
|
|
|
/* If we are in AArch32 mode then we need to sync the AArch32 regs with the
|
|
|
|
* incoming AArch64 regs received from 64-bit KVM.
|
|
|
|
* We must perform this after all of the registers have been acquired from
|
|
|
|
* the kernel.
|
|
|
|
*/
|
|
|
|
if (!is_a64(env)) {
|
|
|
|
aarch64_sync_64_to_32(env);
|
|
|
|
}
|
|
|
|
|
2014-04-15 20:18:42 +02:00
|
|
|
reg.id = AARCH64_CORE_REG(elr_el1);
|
2014-05-27 18:09:51 +02:00
|
|
|
reg.addr = (uintptr_t) &env->elr_el[1];
|
2014-04-15 20:18:42 +02:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-04-01 18:57:30 +02:00
|
|
|
/* Fetch the SPSR registers
|
|
|
|
*
|
|
|
|
* KVM SPSRs 0-4 map to QEMU banks 1-5
|
|
|
|
*/
|
2014-04-15 20:18:43 +02:00
|
|
|
for (i = 0; i < KVM_NR_SPSR; i++) {
|
|
|
|
reg.id = AARCH64_CORE_REG(spsr[i]);
|
2015-04-01 18:57:30 +02:00
|
|
|
reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
|
2014-04-15 20:18:43 +02:00
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-01 18:57:30 +02:00
|
|
|
el = arm_current_el(env);
|
|
|
|
if (el > 0 && !is_a64(env)) {
|
|
|
|
i = bank_number(env->uncached_cpsr & CPSR_M);
|
|
|
|
env->spsr = env->banked_spsr[i];
|
|
|
|
}
|
|
|
|
|
2019-10-31 15:27:30 +01:00
|
|
|
if (cpu_isar_feature(aa64_sve, cpu)) {
|
|
|
|
ret = kvm_arch_get_sve(cs);
|
|
|
|
} else {
|
|
|
|
ret = kvm_arch_get_fpsimd(cs);
|
|
|
|
}
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg.addr = (uintptr_t)(&fpr);
|
|
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
vfp_set_fpsr(env, fpr);
|
|
|
|
|
|
|
|
reg.addr = (uintptr_t)(&fpr);
|
|
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
2015-04-01 18:57:30 +02:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
2019-10-31 15:27:30 +01:00
|
|
|
vfp_set_fpcr(env, fpr);
|
2015-04-01 18:57:30 +02:00
|
|
|
|
2018-10-24 08:50:16 +02:00
|
|
|
ret = kvm_get_vcpu_events(cpu);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-02-05 14:37:25 +01:00
|
|
|
if (!write_kvmstate_to_list(cpu)) {
|
2019-08-02 14:25:34 +02:00
|
|
|
return -EINVAL;
|
2015-02-05 14:37:25 +01:00
|
|
|
}
|
|
|
|
/* Note that it's OK to have registers which aren't in CPUState,
|
|
|
|
* so we can ignore a failure return here.
|
|
|
|
*/
|
|
|
|
write_list_to_cpustate(cpu);
|
|
|
|
|
2015-04-01 18:57:30 +02:00
|
|
|
kvm_arm_sync_mpstate_to_qemu(cpu);
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
/* TODO: other registers */
|
|
|
|
return ret;
|
|
|
|
}
|
2015-12-17 14:37:15 +01:00
|
|
|
|
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
External Abort(SEA). Then host kernel gets an APEI notification and calls
memory_failure() to unmapped the affected page in stage 2, finally
returns to guest.
Guest continues to access the PG_hwpoison page, it will trap to KVM as
stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
Qemu, Qemu records this error address into guest APEI GHES memory and
notifes guest using Synchronous-External-Abort(SEA).
In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function
in which we can setup the type of exception and the syndrome information.
When switching to guest, the target vcpu will jump to the synchronous
external abort vector table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the
ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
not valid and hold an UNKNOWN value. These values will be set to KVM
register structures through KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20200512030609.19593-10-gengdongjiu@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-12 05:06:08 +02:00
|
|
|
void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
|
|
|
|
{
|
|
|
|
ram_addr_t ram_addr;
|
|
|
|
hwaddr paddr;
|
|
|
|
|
|
|
|
assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
|
|
|
|
|
2021-06-17 14:24:38 +02:00
|
|
|
if (acpi_ghes_present() && addr) {
|
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
External Abort(SEA). Then host kernel gets an APEI notification and calls
memory_failure() to unmapped the affected page in stage 2, finally
returns to guest.
Guest continues to access the PG_hwpoison page, it will trap to KVM as
stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
Qemu, Qemu records this error address into guest APEI GHES memory and
notifes guest using Synchronous-External-Abort(SEA).
In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function
in which we can setup the type of exception and the syndrome information.
When switching to guest, the target vcpu will jump to the synchronous
external abort vector table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the
ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
not valid and hold an UNKNOWN value. These values will be set to KVM
register structures through KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Xiang Zheng <zhengxiang9@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20200512030609.19593-10-gengdongjiu@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-12 05:06:08 +02:00
|
|
|
ram_addr = qemu_ram_addr_from_host(addr);
|
|
|
|
if (ram_addr != RAM_ADDR_INVALID &&
|
|
|
|
kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
|
|
|
|
kvm_hwpoison_page_add(ram_addr);
|
|
|
|
/*
|
|
|
|
* If this is a BUS_MCEERR_AR, we know we have been called
|
|
|
|
* synchronously from the vCPU thread, so we can easily
|
|
|
|
* synchronize the state and inject an error.
|
|
|
|
*
|
|
|
|
* TODO: we currently don't tell the guest at all about
|
|
|
|
* BUS_MCEERR_AO. In that case we might either be being
|
|
|
|
* called synchronously from the vCPU thread, or a bit
|
|
|
|
* later from the main thread, so doing the injection of
|
|
|
|
* the error would be more complicated.
|
|
|
|
*/
|
|
|
|
if (code == BUS_MCEERR_AR) {
|
|
|
|
kvm_cpu_synchronize_state(c);
|
|
|
|
if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr)) {
|
|
|
|
kvm_inject_arm_sea(c);
|
|
|
|
} else {
|
|
|
|
error_report("failed to record the error");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (code == BUS_MCEERR_AO) {
|
|
|
|
error_report("Hardware memory error at addr %p for memory used by "
|
|
|
|
"QEMU itself instead of guest system!", addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (code == BUS_MCEERR_AR) {
|
|
|
|
error_report("Hardware memory error!");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-17 14:37:15 +01:00
|
|
|
/* C6.6.29 BRK instruction */
|
|
|
|
static const uint32_t brk_insn = 0xd4200000;
|
|
|
|
|
|
|
|
int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
|
|
|
|
{
|
|
|
|
if (have_guest_debug) {
|
|
|
|
if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) ||
|
|
|
|
cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
error_report("guest debug not supported on this kernel");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
|
|
|
|
{
|
|
|
|
static uint32_t brk;
|
|
|
|
|
|
|
|
if (have_guest_debug) {
|
|
|
|
if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) ||
|
|
|
|
brk != brk_insn ||
|
|
|
|
cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
error_report("guest debug not supported on this kernel");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register
|
|
|
|
*
|
|
|
|
* To minimise translating between kernel and user-space the kernel
|
|
|
|
* ABI just provides user-space with the full exception syndrome
|
|
|
|
* register value to be decoded in QEMU.
|
|
|
|
*/
|
|
|
|
|
|
|
|
bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
|
|
|
|
{
|
2018-10-24 08:50:18 +02:00
|
|
|
int hsr_ec = syn_get_ec(debug_exit->hsr);
|
2015-12-17 14:37:15 +01:00
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
|
|
|
|
/* Ensure PC is synchronised */
|
|
|
|
kvm_cpu_synchronize_state(cs);
|
|
|
|
|
|
|
|
switch (hsr_ec) {
|
2015-12-17 14:37:15 +01:00
|
|
|
case EC_SOFTWARESTEP:
|
|
|
|
if (cs->singlestep_enabled) {
|
|
|
|
return true;
|
|
|
|
} else {
|
2015-12-17 14:37:15 +01:00
|
|
|
/*
|
|
|
|
* The kernel should have suppressed the guest's ability to
|
|
|
|
* single step at this point so something has gone wrong.
|
|
|
|
*/
|
|
|
|
error_report("%s: guest single-step while debugging unsupported"
|
2017-04-20 18:32:29 +02:00
|
|
|
" (%"PRIx64", %"PRIx32")",
|
2015-12-17 14:37:15 +01:00
|
|
|
__func__, env->pc, debug_exit->hsr);
|
|
|
|
return false;
|
2015-12-17 14:37:15 +01:00
|
|
|
}
|
|
|
|
break;
|
2015-12-17 14:37:15 +01:00
|
|
|
case EC_AA64_BKPT:
|
|
|
|
if (kvm_find_sw_breakpoint(cs, env->pc)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
2015-12-17 14:37:15 +01:00
|
|
|
case EC_BREAKPOINT:
|
|
|
|
if (find_hw_breakpoint(cs, env->pc)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case EC_WATCHPOINT:
|
|
|
|
{
|
|
|
|
CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far);
|
|
|
|
if (wp) {
|
|
|
|
cs->watchpoint_hit = wp;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2015-12-17 14:37:15 +01:00
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")",
|
2015-12-17 14:37:15 +01:00
|
|
|
__func__, debug_exit->hsr, env->pc);
|
|
|
|
}
|
|
|
|
|
2015-12-17 14:37:15 +01:00
|
|
|
/* If we are not handling the debug exception it must belong to
|
|
|
|
* the guest. Let's re-use the existing TCG interrupt code to set
|
|
|
|
* everything up properly.
|
|
|
|
*/
|
|
|
|
cs->exception_index = EXCP_BKPT;
|
|
|
|
env->exception.syndrome = debug_exit->hsr;
|
|
|
|
env->exception.vaddress = debug_exit->far;
|
2018-11-13 11:47:59 +01:00
|
|
|
env->exception.target_el = 1;
|
2018-11-13 11:47:59 +01:00
|
|
|
qemu_mutex_lock_iothread();
|
2021-02-04 17:39:16 +01:00
|
|
|
arm_cpu_do_interrupt(cs);
|
2018-11-13 11:47:59 +01:00
|
|
|
qemu_mutex_unlock_iothread();
|
2015-12-17 14:37:15 +01:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
2020-07-03 17:59:42 +02:00
|
|
|
|
|
|
|
#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
|
|
|
|
#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ESR_EL1
|
|
|
|
* ISS encoding
|
|
|
|
* AARCH64: DFSC, bits [5:0]
|
|
|
|
* AARCH32:
|
|
|
|
* TTBCR.EAE == 0
|
|
|
|
* FS[4] - DFSR[10]
|
|
|
|
* FS[3:0] - DFSR[3:0]
|
|
|
|
* TTBCR.EAE == 1
|
|
|
|
* FS, bits [5:0]
|
|
|
|
*/
|
|
|
|
#define ESR_DFSC(aarch64, lpae, v) \
|
|
|
|
((aarch64 || (lpae)) ? ((v) & 0x3F) \
|
|
|
|
: (((v) >> 6) | ((v) & 0x1F)))
|
|
|
|
|
|
|
|
#define ESR_DFSC_EXTABT(aarch64, lpae) \
|
|
|
|
((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
|
|
|
|
|
|
|
|
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
|
|
|
|
{
|
|
|
|
uint64_t dfsr_val;
|
|
|
|
|
|
|
|
if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
|
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
|
|
|
|
int lpae = 0;
|
|
|
|
|
|
|
|
if (!aarch64_mode) {
|
|
|
|
uint64_t ttbcr;
|
|
|
|
|
|
|
|
if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
|
|
|
|
lpae = arm_feature(env, ARM_FEATURE_LPAE)
|
|
|
|
&& (ttbcr & TTBCR_EAE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* The verification here is based on the DFSC bits
|
|
|
|
* of the ESR_EL1 reg only
|
|
|
|
*/
|
|
|
|
return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
|
|
|
|
ESR_DFSC_EXTABT(aarch64_mode, lpae));
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|