351 lines
10 KiB
Plaintext
351 lines
10 KiB
Plaintext
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/*
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* Copyright (c) 2020 Xilinx Inc.
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/ {
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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compatible = "xlnx,microblaze";
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model = "edk131";
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memory@50000000 {
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device_type = "memory";
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reg = < 0x50000000 0x10000000 >;
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};
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aliases {
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ethernet0 = "/axi/axi-ethernet@82780000";
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serial0 = "/axi/serial@83e00000";
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};
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chosen {
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bootargs = " console=ttyS0,115200 ";
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stdout-path = "/axi/serial@83e00000";
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};
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cpus {
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#address-cells = < 0x01 >;
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#cpus = < 0x01 >;
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#size-cells = < 0x00 >;
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cpu@0 {
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clock-frequency = < 0xbebc200 >;
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compatible = "xlnx,microblaze-8.10.a";
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d-cache-baseaddr = < 0x50000000 >;
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d-cache-highaddr = < 0x5fffffff >;
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d-cache-line-size = < 0x20 >;
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d-cache-size = < 0x800 >;
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device_type = "cpu";
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i-cache-baseaddr = < 0x50000000 >;
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i-cache-highaddr = < 0x5fffffff >;
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i-cache-line-size = < 0x20 >;
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i-cache-size = < 0x800 >;
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model = "microblaze,8.10.a";
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reg = < 0x00 >;
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timebase-frequency = < 0xbebc200 >;
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xlnx,addr-tag-bits = < 0x11 >;
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xlnx,allow-dcache-wr = < 0x01 >;
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xlnx,allow-icache-wr = < 0x01 >;
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xlnx,area-optimized = < 0x00 >;
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xlnx,branch-target-cache-size = < 0x00 >;
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xlnx,cache-byte-size = < 0x800 >;
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xlnx,d-axi = < 0x01 >;
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xlnx,d-lmb = < 0x01 >;
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xlnx,d-plb = < 0x00 >;
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xlnx,data-size = < 0x20 >;
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xlnx,dcache-addr-tag = < 0x11 >;
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xlnx,dcache-always-used = < 0x01 >;
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xlnx,dcache-byte-size = < 0x800 >;
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xlnx,dcache-data-width = < 0x00 >;
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xlnx,dcache-force-tag-lutram = < 0x00 >;
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xlnx,dcache-interface = < 0x01 >;
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xlnx,dcache-line-len = < 0x08 >;
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xlnx,dcache-use-fsl = < 0x00 >;
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xlnx,dcache-use-writeback = < 0x01 >;
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xlnx,dcache-victims = < 0x00 >;
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xlnx,debug-enabled = < 0x01 >;
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xlnx,div-zero-exception = < 0x01 >;
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xlnx,dynamic-bus-sizing = < 0x01 >;
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xlnx,ecc-use-ce-exception = < 0x00 >;
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xlnx,edge-is-positive = < 0x01 >;
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xlnx,endianness = < 0x01 >;
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xlnx,family = "virtex6";
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xlnx,fault-tolerant = < 0x00 >;
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xlnx,fpu-exception = < 0x01 >;
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xlnx,freq = < 0xbebc200 >;
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xlnx,fsl-data-size = < 0x20 >;
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xlnx,fsl-exception = < 0x00 >;
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xlnx,fsl-links = < 0x00 >;
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xlnx,i-axi = < 0x01 >;
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xlnx,i-lmb = < 0x01 >;
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xlnx,i-plb = < 0x00 >;
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xlnx,icache-always-used = < 0x01 >;
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xlnx,icache-data-width = < 0x00 >;
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xlnx,icache-force-tag-lutram = < 0x00 >;
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xlnx,icache-interface = < 0x00 >;
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xlnx,icache-line-len = < 0x08 >;
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xlnx,icache-streams = < 0x00 >;
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xlnx,icache-use-fsl = < 0x00 >;
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xlnx,icache-victims = < 0x00 >;
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xlnx,ill-opcode-exception = < 0x01 >;
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xlnx,instance = "microblaze_0";
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xlnx,interconnect = < 0x02 >;
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xlnx,interrupt-is-edge = < 0x00 >;
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xlnx,mmu-dtlb-size = < 0x04 >;
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xlnx,mmu-itlb-size = < 0x02 >;
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xlnx,mmu-privileged-instr = < 0x00 >;
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xlnx,mmu-tlb-access = < 0x03 >;
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xlnx,mmu-zones = < 0x02 >;
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xlnx,number-of-pc-brk = < 0x01 >;
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xlnx,number-of-rd-addr-brk = < 0x00 >;
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xlnx,number-of-wr-addr-brk = < 0x00 >;
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xlnx,opcode-0x0-illegal = < 0x01 >;
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xlnx,optimization = < 0x00 >;
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xlnx,pvr = < 0x02 >;
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xlnx,pvr-user1 = < 0x00 >;
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xlnx,pvr-user2 = < 0x00 >;
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xlnx,reset-msr = < 0x00 >;
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xlnx,sco = < 0x00 >;
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xlnx,stream-interconnect = < 0x00 >;
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xlnx,unaligned-exceptions = < 0x01 >;
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xlnx,use-barrel = < 0x01 >;
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xlnx,use-branch-target-cache = < 0x00 >;
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xlnx,use-dcache = < 0x01 >;
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xlnx,use-div = < 0x01 >;
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xlnx,use-ext-brk = < 0x01 >;
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xlnx,use-ext-nm-brk = < 0x01 >;
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xlnx,use-extended-fsl-instr = < 0x00 >;
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xlnx,use-fpu = < 0x01 >;
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xlnx,use-hw-mul = < 0x02 >;
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xlnx,use-icache = < 0x01 >;
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xlnx,use-interrupt = < 0x01 >;
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xlnx,use-mmu = < 0x03 >;
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xlnx,use-msr-instr = < 0x01 >;
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xlnx,use-pcmp-instr = < 0x01 >;
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xlnx,use-stack-protection = < 0x00 >;
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};
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};
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axi {
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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compatible = "xlnx,axi-interconnect-1.02.a\0simple-bus";
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ranges;
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axi-ethernet@82780000 {
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axistream-connected = < &axi_dma >;
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compatible = "xlnx,axi-ethernet-2.01.a\0xlnx,axi-ethernet-1.00.a";
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device_type = "network";
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interrupt-parent = < &intc >;
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interrupts = < 0x03 0x02 >;
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local-mac-address = [ 00 0a 35 00 22 01 ];
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phy-handle = < &phy7 >;
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reg = < 0x82780000 0x40000 >;
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xlnx,avb = < 0x00 >;
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xlnx,halfdup = < 0x00 >;
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xlnx,include-io = < 0x01 >;
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xlnx,mcast-extend = < 0x00 >;
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xlnx,phy-type = < 0x01 >;
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xlnx,phyaddr = "0B00001";
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xlnx,rxcsum = < 0x00 >;
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xlnx,rxmem = < 0x1000 >;
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xlnx,rxvlan-strp = < 0x00 >;
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xlnx,rxvlan-tag = < 0x00 >;
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xlnx,rxvlan-tran = < 0x00 >;
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xlnx,stats = < 0x00 >;
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xlnx,txcsum = < 0x00 >;
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xlnx,txmem = < 0x1000 >;
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xlnx,txvlan-strp = < 0x00 >;
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xlnx,txvlan-tag = < 0x00 >;
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xlnx,txvlan-tran = < 0x00 >;
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xlnx,type = < 0x02 >;
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mdio {
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#address-cells = < 0x01 >;
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#size-cells = < 0x00 >;
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phy7: phy@7 {
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compatible = "marvell,88e1111";
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device_type = "ethernet-phy";
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reg = < 0x07 >;
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};
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};
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};
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axi_dma: axi-dma@84600000 {
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compatible = "xlnx,axi-dma-3.00.a";
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interrupt-parent = < &intc >;
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interrupts = < 0x01 0x02 0x00 0x02 >;
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reg = < 0x84600000 0x10000 >;
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xlnx,dlytmr-resolution = < 0x4e2 >;
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xlnx,family = "virtex6";
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xlnx,include-mm2s = < 0x01 >;
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xlnx,include-mm2s-dre = < 0x01 >;
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xlnx,include-s2mm = < 0x01 >;
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xlnx,include-s2mm-dre = < 0x01 >;
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xlnx,mm2s-burst-size = < 0x10 >;
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xlnx,prmry-is-aclk-async = < 0x00 >;
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xlnx,s2mm-burst-size = < 0x10 >;
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xlnx,sg-include-desc-queue = < 0x01 >;
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xlnx,sg-include-stscntrl-strm = < 0x01 >;
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xlnx,sg-length-width = < 0x10 >;
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xlnx,sg-use-stsapp-length = < 0x01 >;
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};
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serial@83e00000 {
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clock-frequency = < 0x5f5e100 >;
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compatible = "xlnx,axi-uart16550-1.01.a\0xlnx,xps-uart16550-2.00.a\0ns16550a";
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current-speed = < 0x2580 >;
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device_type = "serial";
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interrupt-parent = < &intc >;
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interrupts = < 0x05 0x02 >;
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reg = < 0x83e00000 0x10000 >;
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reg-offset = < 0x1000 >;
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reg-shift = < 0x02 >;
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xlnx,external-xin-clk-hz = < 0x17d7840 >;
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xlnx,family = "virtex6";
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xlnx,has-external-rclk = < 0x00 >;
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xlnx,has-external-xin = < 0x00 >;
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xlnx,is-a-16550 = < 0x01 >;
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xlnx,use-modem-ports = < 0x00 >;
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xlnx,use-user-ports = < 0x00 >;
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};
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system-timer@83c00000 {
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clock-frequency = < 0x5f5e100 >;
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compatible = "xlnx,axi-timer-1.01.a\0xlnx,xps-timer-1.00.a";
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interrupt-parent = < &intc >;
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interrupts = < 0x02 0x00 >;
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reg = < 0x83c00000 0x10000 >;
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xlnx,count-width = < 0x20 >;
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xlnx,family = "virtex6";
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xlnx,gen0-assert = < 0x01 >;
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xlnx,gen1-assert = < 0x01 >;
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xlnx,one-timer-only = < 0x00 >;
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xlnx,trig0-assert = < 0x01 >;
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xlnx,trig1-assert = < 0x01 >;
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};
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intc: interrupt-controller@81800000 {
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#interrupt-cells = < 0x02 >;
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compatible = "xlnx,axi-intc-1.01.a\0xlnx,xps-intc-1.00.a";
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interrupt-controller;
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reg = < 0x81800000 0x10000 >;
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xlnx,kind-of-intr = < 0x04 >;
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xlnx,num-intr-inputs = < 0x06 >;
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};
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flash@86000000 {
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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bank-width = < 0x02 >;
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compatible = "xlnx,axi-emc-1.01.a\0cfi-flash";
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reg = < 0x86000000 0x2000000 >;
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xlnx,axi-clk-period-ps = < 0x2710 >;
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xlnx,family = "virtex6";
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xlnx,include-datawidth-matching-0 = < 0x01 >;
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xlnx,include-datawidth-matching-1 = < 0x00 >;
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xlnx,include-datawidth-matching-2 = < 0x00 >;
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xlnx,include-datawidth-matching-3 = < 0x00 >;
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xlnx,include-negedge-ioregs = < 0x00 >;
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xlnx,max-mem-width = < 0x10 >;
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xlnx,mem0-type = < 0x02 >;
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xlnx,mem0-width = < 0x10 >;
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xlnx,mem1-type = < 0x00 >;
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xlnx,mem1-width = < 0x20 >;
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xlnx,mem2-type = < 0x00 >;
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xlnx,mem2-width = < 0x20 >;
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xlnx,mem3-type = < 0x00 >;
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xlnx,mem3-width = < 0x20 >;
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xlnx,num-banks-mem = < 0x01 >;
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xlnx,parity-type-mem-0 = < 0x00 >;
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xlnx,parity-type-mem-1 = < 0x00 >;
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xlnx,parity-type-mem-2 = < 0x00 >;
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xlnx,parity-type-mem-3 = < 0x00 >;
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xlnx,s-axi-en-reg = < 0x00 >;
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xlnx,s-axi-mem-addr-width = < 0x20 >;
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xlnx,s-axi-mem-data-width = < 0x20 >;
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xlnx,s-axi-mem-id-width = < 0x01 >;
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xlnx,s-axi-mem-protocol = "AXI4LITE";
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xlnx,s-axi-reg-addr-width = < 0x20 >;
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xlnx,s-axi-reg-data-width = < 0x20 >;
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xlnx,s-axi-reg-protocol = "axi4";
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xlnx,synch-pipedelay-0 = < 0x02 >;
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xlnx,synch-pipedelay-1 = < 0x02 >;
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xlnx,synch-pipedelay-2 = < 0x02 >;
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xlnx,synch-pipedelay-3 = < 0x02 >;
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xlnx,tavdv-ps-mem-0 = < 0x1fbd0 >;
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xlnx,tavdv-ps-mem-1 = < 0x3a98 >;
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xlnx,tavdv-ps-mem-2 = < 0x3a98 >;
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xlnx,tavdv-ps-mem-3 = < 0x3a98 >;
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xlnx,tcedv-ps-mem-0 = < 0x1fbd0 >;
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xlnx,tcedv-ps-mem-1 = < 0x3a98 >;
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xlnx,tcedv-ps-mem-2 = < 0x3a98 >;
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xlnx,tcedv-ps-mem-3 = < 0x3a98 >;
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xlnx,thzce-ps-mem-0 = < 0x88b8 >;
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xlnx,thzce-ps-mem-1 = < 0x1b58 >;
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xlnx,thzce-ps-mem-2 = < 0x1b58 >;
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xlnx,thzce-ps-mem-3 = < 0x1b58 >;
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xlnx,thzoe-ps-mem-0 = < 0x1b58 >;
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xlnx,thzoe-ps-mem-1 = < 0x1b58 >;
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|
|
xlnx,thzoe-ps-mem-2 = < 0x1b58 >;
|
||
|
|
xlnx,thzoe-ps-mem-3 = < 0x1b58 >;
|
||
|
|
xlnx,tlzwe-ps-mem-0 = < 0x88b8 >;
|
||
|
|
xlnx,tlzwe-ps-mem-1 = < 0x00 >;
|
||
|
|
xlnx,tlzwe-ps-mem-2 = < 0x00 >;
|
||
|
|
xlnx,tlzwe-ps-mem-3 = < 0x00 >;
|
||
|
|
xlnx,tpacc-ps-flash-0 = < 0x61a8 >;
|
||
|
|
xlnx,tpacc-ps-flash-1 = < 0x61a8 >;
|
||
|
|
xlnx,tpacc-ps-flash-2 = < 0x61a8 >;
|
||
|
|
xlnx,tpacc-ps-flash-3 = < 0x61a8 >;
|
||
|
|
xlnx,twc-ps-mem-0 = < 0x32c8 >;
|
||
|
|
xlnx,twc-ps-mem-1 = < 0x3a98 >;
|
||
|
|
xlnx,twc-ps-mem-2 = < 0x3a98 >;
|
||
|
|
xlnx,twc-ps-mem-3 = < 0x3a98 >;
|
||
|
|
xlnx,twp-ps-mem-0 = < 0x11170 >;
|
||
|
|
xlnx,twp-ps-mem-1 = < 0x2ee0 >;
|
||
|
|
xlnx,twp-ps-mem-2 = < 0x2ee0 >;
|
||
|
|
xlnx,twp-ps-mem-3 = < 0x2ee0 >;
|
||
|
|
xlnx,twph-ps-mem-0 = < 0x2ee0 >;
|
||
|
|
xlnx,twph-ps-mem-1 = < 0x2ee0 >;
|
||
|
|
xlnx,twph-ps-mem-2 = < 0x2ee0 >;
|
||
|
|
xlnx,twph-ps-mem-3 = < 0x2ee0 >;
|
||
|
|
|
||
|
|
partition@0 {
|
||
|
|
label = "fpga";
|
||
|
|
reg = < 0x00 0x100000 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
partition@100000 {
|
||
|
|
label = "boot";
|
||
|
|
reg = < 0x100000 0x40000 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
partition@140000 {
|
||
|
|
label = "bootenv";
|
||
|
|
reg = < 0x140000 0x20000 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
partition@160000 {
|
||
|
|
label = "config";
|
||
|
|
reg = < 0x160000 0x20000 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
partition@180000 {
|
||
|
|
label = "image";
|
||
|
|
reg = < 0x180000 0xa00000 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
partition@b80000 {
|
||
|
|
label = "spare";
|
||
|
|
reg = < 0xb80000 0x00 >;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|