qemu-e2k/tcg/arm/tcg-target-con-str.h

/* SPDX-License-Identifier: MIT */
/*
 * Define Arm target-specific operand constraints.
 * Copyright (c) 2021 Linaro
 */

/*
 * Define constraint letters for register sets:
 * REGS(letter, register_mask)
 */
REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
REGS('r', ALL_GENERAL_REGS)
REGS('q', ALL_QLDST_REGS)
REGS('Q', ALL_QLDST_REGS & 0x5555)   /* even qldst */
REGS('w', ALL_VECTOR_REGS)

/*
 * Define constraint letters for constants:
 * CONST(letter, TCG_CT_CONST_* bit set)
 */
CONST('I', TCG_CT_CONST_ARM)
CONST('K', TCG_CT_CONST_INV)
CONST('N', TCG_CT_CONST_NEG)
CONST('O', TCG_CT_CONST_ORRI)
CONST('V', TCG_CT_CONST_ANDI)
CONST('Z', TCG_CT_CONST_ZERO)
tcg/arm: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-15 20:53:54 +02:00			`/* SPDX-License-Identifier: MIT */`
			`/*`
			`* Define Arm target-specific operand constraints.`
			`* Copyright (c) 2021 Linaro`
			`*/`

			`/*`
			`* Define constraint letters for register sets:`
			`* REGS(letter, register_mask)`
			`*/`
tcg/arm: Use register pair allocation for qemu_{ld,st}_i64 Although we still can't use ldrd and strd for all operations, increase the chances by getting the register allocation correct. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-10-14 02:24:52 +02:00			`REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */`
tcg/arm: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-15 20:53:54 +02:00			`REGS('r', ALL_GENERAL_REGS)`
tcg/arm: Adjust constraints on qemu_ld/st Always reserve r3 for tlb softmmu lookup. Fix a bug in user-only ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads to the misaligned trap. Remove r0+r1 from user-only ALL_QLDST_REGS; I believe these had been reserved for bswap, which we no longer perform during qemu_st. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2023-04-24 13:31:46 +02:00			`REGS('q', ALL_QLDST_REGS)`
			`REGS('Q', ALL_QLDST_REGS & 0x5555) /* even qldst */`
tcg/arm: Add host vector framework Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2021-05-04 01:47:52 +02:00			`REGS('w', ALL_VECTOR_REGS)`
tcg/arm: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-15 20:53:54 +02:00
			`/*`
			`* Define constraint letters for constants:`
			`* CONST(letter, TCG_CT_CONST_* bit set)`
			`*/`
			`CONST('I', TCG_CT_CONST_ARM)`
			`CONST('K', TCG_CT_CONST_INV)`
			`CONST('N', TCG_CT_CONST_NEG)`
tcg/arm: Implement minimal vector operations Implementing dup2, add, sub, and, or, xor as the minimal set. This allows us to actually enable neon in the header file. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-09-06 00:54:33 +02:00			`CONST('O', TCG_CT_CONST_ORRI)`
			`CONST('V', TCG_CT_CONST_ANDI)`
tcg/arm: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-15 20:53:54 +02:00			`CONST('Z', TCG_CT_CONST_ZERO)`