docs: explain effect of smp_read_barrier_depends() on modern architectures
The documentation for smp_read_barrier_depends() does not mention the architectures for which it is an optimization, for example ARM and PPC. As a result, it is not clear to the reader why one would use it. Relegate Alpha to a footnote together with other architectures where it is equivalent to smp_rmb(). Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -220,10 +220,9 @@ They come in six kinds:
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retrieves the address to which the second load will be directed),
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the processor will guarantee that the first LOAD will appear to happen
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before the second with respect to the other components of the system.
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However, this is not always true---for example, it was not true on
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Alpha processors. Whenever this kind of access happens to shared
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memory (that is not protected by a lock), a read barrier is needed,
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and ``smp_read_barrier_depends()`` can be used instead of ``smp_rmb()``.
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Therefore, unlike ``smp_rmb()`` or ``qatomic_load_acquire()``,
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``smp_read_barrier_depends()`` can be just a compiler barrier on
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weakly-ordered architectures such as Arm or PPC[#]_.
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Note that the first load really has to have a _data_ dependency and not
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a control dependency. If the address for the second load is dependent
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@ -231,6 +230,10 @@ They come in six kinds:
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than actually loading the address itself, then it's a _control_
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dependency and a full read barrier or better is required.
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.. [#] The DEC Alpha is an exception, because ``smp_read_barrier_depends()``
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needs a processor barrier. On strongly-ordered architectures such
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as x86 or s390, ``smp_rmb()`` and ``qatomic_load_acquire()`` can
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also be compiler barriers only.
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Memory barriers and ``qatomic_load_acquire``/``qatomic_store_release`` are
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mostly used when a data structure has one thread that is always a writer
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