Rearrange slavio_misc code to prepare for different addresses
Pass first env instead of using cpu_single_env directly Add Aux1 to Sun4c git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3934 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
67e42751dc
commit
0019ad5346
216
hw/slavio_misc.c
216
hw/slavio_misc.c
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@ -50,7 +50,7 @@ typedef struct MiscState {
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uint8_t diag, mctrl;
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uint32_t sysctrl;
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uint16_t leds;
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target_phys_addr_t power_base;
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CPUState *env;
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} MiscState;
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#define MISC_SIZE 1
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@ -62,8 +62,6 @@ typedef struct MiscState {
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#define MISC_MASK 0x0fff0000
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#define MISC_LEDS 0x01600000
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#define MISC_CFG 0x01800000
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#define MISC_AUX1 0x01900000
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#define MISC_AUX2 0x01910000
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#define MISC_DIAG 0x01a00000
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#define MISC_MDM 0x01b00000
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#define MISC_SYS 0x01f00000
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@ -122,21 +120,6 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
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s->config = val & 0xff;
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slavio_misc_update_irq(s);
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break;
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case MISC_AUX1:
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MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
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s->aux1 = val & 0xff;
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break;
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case MISC_AUX2:
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val &= AUX2_PWRINTCLR | AUX2_PWROFF;
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MISC_DPRINTF("Write aux2 %2.2x\n", val);
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val |= s->aux2 & AUX2_PWRFAIL;
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if (val & AUX2_PWRINTCLR) // Clear Power Fail int
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val &= AUX2_PWROFF;
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s->aux2 = val;
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if (val & AUX2_PWROFF)
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qemu_system_shutdown_request();
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slavio_misc_update_irq(s);
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break;
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case MISC_DIAG:
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MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
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s->diag = val & 0xff;
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@ -146,10 +129,6 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
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s->mctrl = val & 0xff;
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break;
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default:
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if (addr == s->power_base) {
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MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
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}
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break;
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}
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}
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@ -164,14 +143,6 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
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ret = s->config;
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MISC_DPRINTF("Read config %2.2x\n", ret);
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break;
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case MISC_AUX1:
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ret = s->aux1;
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MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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break;
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case MISC_AUX2:
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ret = s->aux2;
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MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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break;
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case MISC_DIAG:
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ret = s->diag;
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MISC_DPRINTF("Read diag %2.2x\n", ret);
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@ -181,9 +152,6 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
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MISC_DPRINTF("Read modem control %2.2x\n", ret);
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break;
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default:
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if (addr == s->power_base) {
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MISC_DPRINTF("Read power management %2.2x\n", ret);
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}
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break;
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}
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return ret;
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@ -201,6 +169,105 @@ static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
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NULL,
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};
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static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
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s->aux1 = val & 0xff;
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}
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static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->aux1;
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MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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return ret;
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}
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static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
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slavio_aux1_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
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slavio_aux1_mem_writeb,
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NULL,
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NULL,
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};
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static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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val &= AUX2_PWRINTCLR | AUX2_PWROFF;
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MISC_DPRINTF("Write aux2 %2.2x\n", val);
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val |= s->aux2 & AUX2_PWRFAIL;
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if (val & AUX2_PWRINTCLR) // Clear Power Fail int
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val &= AUX2_PWROFF;
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s->aux2 = val;
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if (val & AUX2_PWROFF)
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qemu_system_shutdown_request();
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slavio_misc_update_irq(s);
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}
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static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->aux2;
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MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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return ret;
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}
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static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
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slavio_aux2_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
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slavio_aux2_mem_writeb,
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NULL,
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NULL,
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};
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static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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MiscState *s = opaque;
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MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
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cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
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}
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static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = 0;
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MISC_DPRINTF("Read power management %2.2x\n", ret);
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return ret;
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}
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static CPUReadMemoryFunc *apc_mem_read[3] = {
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apc_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *apc_mem_write[3] = {
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apc_mem_writeb,
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NULL,
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NULL,
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};
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static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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@ -338,57 +405,68 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
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}
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void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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qemu_irq irq)
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target_phys_addr_t aux1_base,
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target_phys_addr_t aux2_base, qemu_irq irq,
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CPUState *env)
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{
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int slavio_misc_io_memory;
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int io;
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MiscState *s;
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s = qemu_mallocz(sizeof(MiscState));
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if (!s)
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return NULL;
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/* 8 bit registers */
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slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
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slavio_misc_mem_write, s);
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// Slavio control
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cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE,
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slavio_misc_io_memory);
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// AUX 1
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cpu_register_physical_memory(base + MISC_AUX1, MISC_SIZE,
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slavio_misc_io_memory);
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// AUX 2
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cpu_register_physical_memory(base + MISC_AUX2, MISC_SIZE,
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slavio_misc_io_memory);
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// Diagnostics
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cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE,
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slavio_misc_io_memory);
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// Modem control
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cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE,
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slavio_misc_io_memory);
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// Power management
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cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
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s->power_base = power_base;
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if (base) {
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/* 8 bit registers */
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io = cpu_register_io_memory(0, slavio_misc_mem_read,
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slavio_misc_mem_write, s);
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// Slavio control
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cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
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// Diagnostics
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cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
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// Modem control
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cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
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/* 16 bit registers */
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slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
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slavio_led_mem_write, s);
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/* ss600mp diag LEDs */
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cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE,
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slavio_misc_io_memory);
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/* 16 bit registers */
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io = cpu_register_io_memory(0, slavio_led_mem_read,
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slavio_led_mem_write, s);
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/* ss600mp diag LEDs */
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cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
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/* 32 bit registers */
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slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
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slavio_sysctrl_mem_write,
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s);
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// System control
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cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE,
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slavio_misc_io_memory);
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/* 32 bit registers */
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io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
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slavio_sysctrl_mem_write, s);
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// System control
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cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
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}
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// AUX 1 (Misc System Functions)
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if (aux1_base) {
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io = cpu_register_io_memory(0, slavio_aux1_mem_read,
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slavio_aux1_mem_write, s);
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cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
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}
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// AUX 2 (Software Powerdown Control)
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if (aux2_base) {
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io = cpu_register_io_memory(0, slavio_aux2_mem_read,
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slavio_aux2_mem_write, s);
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cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
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}
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// Power management (APC) XXX: not a Slavio device
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if (power_base) {
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io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
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cpu_register_physical_memory(power_base, MISC_SIZE, io);
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}
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s->irq = irq;
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s->env = env;
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register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
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s);
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qemu_register_reset(slavio_misc_reset, s);
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slavio_misc_reset(s);
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return s;
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}
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31
hw/sun4m.c
31
hw/sun4m.c
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@ -83,7 +83,7 @@ struct hwdef {
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
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target_phys_addr_t tcx_base, cs_base, power_base;
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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target_phys_addr_t ecc_base;
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uint32_t ecc_version;
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target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
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@ -515,8 +515,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
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esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
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}
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slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
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slavio_irq[hwdef->me_irq]);
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slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
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hwdef->aux1_base, hwdef->aux2_base,
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slavio_irq[hwdef->me_irq], envs[0]);
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if (hwdef->cs_base != (target_phys_addr_t)-1)
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cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
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@ -662,6 +663,10 @@ static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
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esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
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}
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slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
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hwdef->aux1_base, hwdef->aux2_base,
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slavio_irq[hwdef->me_irq], env);
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kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
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initrd_filename);
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@ -687,7 +692,9 @@ static const struct hwdef hwdefs[] = {
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.power_base = 0x7a000000,
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.apc_base = 0x7a000000, // XXX 0x6a000000,
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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@ -727,7 +734,9 @@ static const struct hwdef hwdefs[] = {
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.dma_base = 0xef0400000ULL,
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.esp_base = 0xef0800000ULL,
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.le_base = 0xef0c00000ULL,
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.power_base = 0xefa000000ULL,
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.aux1_base = 0xff1900000ULL, // XXX 0xff1800000ULL,
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.aux2_base = 0xff1910000ULL, // XXX 0xff1a01000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x10000000, // version 0, implementation 1
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.sun4c_intctl_base = -1,
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@ -769,7 +778,9 @@ static const struct hwdef hwdefs[] = {
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.dma_base = 0xef0081000ULL,
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.esp_base = 0xef0080000ULL,
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.le_base = 0xef0060000ULL,
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.power_base = 0xefa000000ULL,
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.aux1_base = 0xff1900000ULL, // XXX 0xff1800000ULL,
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.aux2_base = 0xff1910000ULL, // XXX should not exist
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x00000000, // version 0, implementation 0
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.sun4c_intctl_base = -1,
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@ -811,7 +822,9 @@ static const struct hwdef hwdefs[] = {
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.dma_base = 0xef0400000ULL,
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.esp_base = 0xef0800000ULL,
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.le_base = 0xef0c00000ULL,
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.power_base = 0xefa000000ULL,
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.aux1_base = 0xff1900000ULL, // XXX 0xff1800000ULL,
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.aux2_base = 0xff1910000ULL, // XXX 0xff1a01000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x20000000, // version 0, implementation 2
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.sun4c_intctl_base = -1,
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@ -852,7 +865,9 @@ static const struct hwdef hwdefs[] = {
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.dma_base = 0xf8400000,
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.esp_base = 0xf8800000,
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.le_base = 0xf8c00000,
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.power_base = -1,
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.apc_base = -1,
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.aux1_base = 0xf7400003,
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.aux2_base = -1,
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.sun4c_intctl_base = 0xf5000000,
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.sun4c_counter_base = 0xf3000000,
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.vram_size = 0x00100000,
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@ -54,7 +54,9 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
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/* slavio_misc.c */
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void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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qemu_irq irq);
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target_phys_addr_t aux1_base,
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target_phys_addr_t aux2_base, qemu_irq irq,
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CPUState *env);
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void slavio_set_power_fail(void *opaque, int power_failing);
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/* esp.c */
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