ppc/xive: add support for the END Event State Buffers
The Event Notification Descriptor (END) XIVE structure also contains two Event State Buffers providing further coalescing of interrupts, one for the notification event (ESn) and one for the escalation events (ESe). A MMIO page is assigned for each to control the EOI through loads only. Stores are not allowed. The END ESBs are modeled through an object resembling the 'XiveSource' It is stateless as the END state bits are backed into the XiveEND structure under the XiveRouter and the MMIO accesses follow the same rules as for the XiveSource ESBs. END ESBs are not supported by the Linux drivers neither on OPAL nor on sPAPR. Nevetherless, it provides a mean to study the question in the future and validates a bit more the XIVE model. Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: Fold in a later fix for field access] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
fcfbc18d00
commit
002686be42
160
hw/intc/xive.c
160
hw/intc/xive.c
@ -613,8 +613,18 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
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* even futher coalescing in the Router
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*/
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if (!xive_end_is_notify(&end)) {
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qemu_log_mask(LOG_UNIMP, "XIVE: !UCOND_NOTIFY not implemented\n");
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return;
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uint8_t pq = xive_get_field32(END_W1_ESn, end.w1);
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bool notify = xive_esb_trigger(&pq);
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if (pq != xive_get_field32(END_W1_ESn, end.w1)) {
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end.w1 = xive_set_field32(END_W1_ESn, end.w1, pq);
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xive_router_write_end(xrtr, end_blk, end_idx, &end, 1);
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}
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/* ESn[Q]=1 : end of notification */
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if (!notify) {
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return;
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}
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}
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/*
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@ -694,6 +704,151 @@ void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon)
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(uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
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}
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/*
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* END ESB MMIO loads
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*/
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static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size)
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{
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XiveENDSource *xsrc = XIVE_END_SOURCE(opaque);
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uint32_t offset = addr & 0xFFF;
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uint8_t end_blk;
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uint32_t end_idx;
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XiveEND end;
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uint32_t end_esmask;
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uint8_t pq;
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uint64_t ret = -1;
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end_blk = xsrc->block_id;
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end_idx = addr >> (xsrc->esb_shift + 1);
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if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
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end_idx);
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return -1;
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}
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if (!xive_end_is_valid(&end)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
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end_blk, end_idx);
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return -1;
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}
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end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe;
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pq = xive_get_field32(end_esmask, end.w1);
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switch (offset) {
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case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF:
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ret = xive_esb_eoi(&pq);
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/* Forward the source event notification for routing ?? */
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break;
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case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF:
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ret = pq;
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break;
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case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
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case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
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case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
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case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
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ret = xive_esb_set(&pq, (offset >> 8) & 0x3);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n",
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offset);
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return -1;
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}
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if (pq != xive_get_field32(end_esmask, end.w1)) {
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end.w1 = xive_set_field32(end_esmask, end.w1, pq);
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xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
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}
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return ret;
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}
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/*
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* END ESB MMIO stores are invalid
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*/
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static void xive_end_source_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%"
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HWADDR_PRIx"\n", addr);
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}
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static const MemoryRegionOps xive_end_source_ops = {
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.read = xive_end_source_read,
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.write = xive_end_source_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 8,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 8,
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.max_access_size = 8,
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},
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};
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static void xive_end_source_realize(DeviceState *dev, Error **errp)
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{
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XiveENDSource *xsrc = XIVE_END_SOURCE(dev);
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Object *obj;
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Error *local_err = NULL;
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obj = object_property_get_link(OBJECT(dev), "xive", &local_err);
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if (!obj) {
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error_propagate(errp, local_err);
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error_prepend(errp, "required link 'xive' not found: ");
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return;
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}
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xsrc->xrtr = XIVE_ROUTER(obj);
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if (!xsrc->nr_ends) {
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error_setg(errp, "Number of interrupt needs to be greater than 0");
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return;
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}
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if (xsrc->esb_shift != XIVE_ESB_4K &&
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xsrc->esb_shift != XIVE_ESB_64K) {
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error_setg(errp, "Invalid ESB shift setting");
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return;
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}
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/*
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* Each END is assigned an even/odd pair of MMIO pages, the even page
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* manages the ESn field while the odd page manages the ESe field.
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*/
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memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc),
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&xive_end_source_ops, xsrc, "xive.end",
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(1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends);
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}
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static Property xive_end_source_properties[] = {
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DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0),
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DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
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DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xive_end_source_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "XIVE END Source";
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dc->props = xive_end_source_properties;
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dc->realize = xive_end_source_realize;
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}
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static const TypeInfo xive_end_source_info = {
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.name = TYPE_XIVE_END_SOURCE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(XiveENDSource),
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.class_init = xive_end_source_class_init,
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};
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/*
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* XIVE Fabric
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*/
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@ -708,6 +863,7 @@ static void xive_register_types(void)
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type_register_static(&xive_source_info);
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type_register_static(&xive_fabric_info);
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type_register_static(&xive_router_info);
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type_register_static(&xive_end_source_info);
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}
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type_init(xive_register_types)
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@ -336,6 +336,27 @@ int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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XiveEND *end, uint8_t word_number);
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/*
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* XIVE END ESBs
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*/
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#define TYPE_XIVE_END_SOURCE "xive-end-source"
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#define XIVE_END_SOURCE(obj) \
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OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE)
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typedef struct XiveENDSource {
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DeviceState parent;
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uint32_t nr_ends;
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uint8_t block_id;
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/* ESB memory region */
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uint32_t esb_shift;
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MemoryRegion esb_mmio;
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XiveRouter *xrtr;
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} XiveENDSource;
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/*
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* For legacy compatibility, the exceptions define up to 256 different
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* priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
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