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target/arm: Restrict tlb flush from vttbr_write to vmid change

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Compare only the VMID field when considering whether we need to flush.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-10 20:18:53 -07:00 committed by Peter Maydell
parent 575a94af3c
commit 00b20ee42e
1 changed files with 2 additions and 2 deletions
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4
target/arm/helper.c
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@ -3815,10 +3815,10 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* A change in VMID to the stage2 page table (Stage2) invalidates
* the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
*/
if (raw_read(env, ri) != value) {
if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
raw_write(env, ri, value);
}
raw_write(env, ri, value);
}
static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {