xilinx: Convert most xilinx devices to MemoryRegion
This converts ethlite, intc, timer and uartlite to use MemoryRegions. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
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@ -50,6 +50,7 @@
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struct xlx_ethlite
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struct xlx_ethlite
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{
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{
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion mmio;
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qemu_irq irq;
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qemu_irq irq;
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NICState *nic;
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NICState *nic;
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NICConf conf;
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NICConf conf;
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@ -70,7 +71,8 @@ static inline void eth_pulse_irq(struct xlx_ethlite *s)
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}
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}
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}
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}
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static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
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static uint64_t
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eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
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{
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{
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struct xlx_ethlite *s = opaque;
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struct xlx_ethlite *s = opaque;
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uint32_t r = 0;
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uint32_t r = 0;
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@ -98,10 +100,12 @@ static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
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}
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}
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static void
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static void
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eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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eth_write(void *opaque, target_phys_addr_t addr,
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uint64_t val64, unsigned int size)
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{
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{
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struct xlx_ethlite *s = opaque;
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struct xlx_ethlite *s = opaque;
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unsigned int base = 0;
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unsigned int base = 0;
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uint32_t value = val64;
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addr >>= 2;
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addr >>= 2;
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switch (addr)
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switch (addr)
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@ -146,12 +150,14 @@ eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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}
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}
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}
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}
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static CPUReadMemoryFunc * const eth_read[] = {
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static const MemoryRegionOps eth_ops = {
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NULL, NULL, ð_readl,
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.read = eth_read,
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};
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.write = eth_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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static CPUWriteMemoryFunc * const eth_write[] = {
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.valid = {
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NULL, NULL, ð_writel,
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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};
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static int eth_can_rx(VLANClientState *nc)
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static int eth_can_rx(VLANClientState *nc)
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@ -206,13 +212,12 @@ static NetClientInfo net_xilinx_ethlite_info = {
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static int xilinx_ethlite_init(SysBusDevice *dev)
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static int xilinx_ethlite_init(SysBusDevice *dev)
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{
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{
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struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
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struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
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int regs;
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(dev, &s->irq);
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s->rxbuf = 0;
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s->rxbuf = 0;
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regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN);
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memory_region_init_io(&s->mmio, ð_ops, s, "xilinx-ethlite", R_MAX * 4);
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sysbus_init_mmio(dev, R_MAX * 4, regs);
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sysbus_init_mmio_region(dev, &s->mmio);
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
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s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
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@ -40,6 +40,7 @@
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struct xlx_pic
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struct xlx_pic
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{
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{
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion mmio;
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qemu_irq parent_irq;
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qemu_irq parent_irq;
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/* Configuration reg chosen at synthesis-time. QEMU populates
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/* Configuration reg chosen at synthesis-time. QEMU populates
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@ -72,7 +73,8 @@ static void update_irq(struct xlx_pic *p)
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}
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}
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}
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}
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static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
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static uint64_t
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pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
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{
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{
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struct xlx_pic *p = opaque;
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struct xlx_pic *p = opaque;
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uint32_t r = 0;
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uint32_t r = 0;
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@ -91,9 +93,11 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
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}
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}
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static void
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static void
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pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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pic_write(void *opaque, target_phys_addr_t addr,
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uint64_t val64, unsigned int size)
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{
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{
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struct xlx_pic *p = opaque;
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struct xlx_pic *p = opaque;
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uint32_t value = val64;
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addr >>= 2;
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addr >>= 2;
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D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
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D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
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@ -116,14 +120,14 @@ pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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update_irq(p);
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update_irq(p);
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}
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}
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static CPUReadMemoryFunc * const pic_read[] = {
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static const MemoryRegionOps pic_ops = {
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NULL, NULL,
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.read = pic_read,
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&pic_readl,
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.write = pic_write,
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};
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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static CPUWriteMemoryFunc * const pic_write[] = {
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.min_access_size = 4,
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NULL, NULL,
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.max_access_size = 4
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&pic_writel,
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}
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};
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};
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static void irq_handler(void *opaque, int irq, int level)
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static void irq_handler(void *opaque, int irq, int level)
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@ -148,13 +152,12 @@ static void irq_handler(void *opaque, int irq, int level)
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static int xilinx_intc_init(SysBusDevice *dev)
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static int xilinx_intc_init(SysBusDevice *dev)
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{
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{
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struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
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struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
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int pic_regs;
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qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
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qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
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sysbus_init_irq(dev, &p->parent_irq);
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sysbus_init_irq(dev, &p->parent_irq);
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pic_regs = cpu_register_io_memory(pic_read, pic_write, p, DEVICE_NATIVE_ENDIAN);
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memory_region_init_io(&p->mmio, &pic_ops, p, "xilinx-pic", R_MAX * 4);
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sysbus_init_mmio(dev, R_MAX * 4, pic_regs);
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sysbus_init_mmio_region(dev, &p->mmio);
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return 0;
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return 0;
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}
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}
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@ -59,6 +59,7 @@ struct xlx_timer
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struct timerblock
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struct timerblock
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{
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{
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion mmio;
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qemu_irq irq;
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qemu_irq irq;
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uint32_t nr_timers;
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uint32_t nr_timers;
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uint32_t freq_hz;
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uint32_t freq_hz;
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@ -85,7 +86,8 @@ static void timer_update_irq(struct timerblock *t)
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qemu_set_irq(t->irq, !!irq);
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qemu_set_irq(t->irq, !!irq);
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}
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}
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static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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static uint64_t
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timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
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{
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{
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struct timerblock *t = opaque;
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struct timerblock *t = opaque;
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struct xlx_timer *xt;
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struct xlx_timer *xt;
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@ -134,11 +136,13 @@ static void timer_enable(struct xlx_timer *xt)
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}
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}
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static void
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static void
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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timer_write(void *opaque, target_phys_addr_t addr,
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uint64_t val64, unsigned int size)
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{
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{
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struct timerblock *t = opaque;
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struct timerblock *t = opaque;
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struct xlx_timer *xt;
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struct xlx_timer *xt;
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unsigned int timer;
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unsigned int timer;
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uint32_t value = val64;
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addr >>= 2;
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addr >>= 2;
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timer = timer_from_addr(addr);
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timer = timer_from_addr(addr);
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@ -166,14 +170,14 @@ timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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timer_update_irq(t);
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timer_update_irq(t);
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}
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}
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static CPUReadMemoryFunc * const timer_read[] = {
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static const MemoryRegionOps timer_ops = {
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NULL, NULL,
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.read = timer_read,
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&timer_readl,
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.write = timer_write,
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};
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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static CPUWriteMemoryFunc * const timer_write[] = {
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.min_access_size = 4,
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NULL, NULL,
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.max_access_size = 4
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&timer_writel,
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}
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};
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};
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static void timer_hit(void *opaque)
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static void timer_hit(void *opaque)
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@ -192,7 +196,6 @@ static int xilinx_timer_init(SysBusDevice *dev)
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{
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{
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struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
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struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
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unsigned int i;
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unsigned int i;
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int timer_regs;
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/* All timers share a single irq line. */
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/* All timers share a single irq line. */
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sysbus_init_irq(dev, &t->irq);
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sysbus_init_irq(dev, &t->irq);
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@ -209,9 +212,9 @@ static int xilinx_timer_init(SysBusDevice *dev)
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ptimer_set_freq(xt->ptimer, t->freq_hz);
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ptimer_set_freq(xt->ptimer, t->freq_hz);
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}
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}
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timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
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memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer",
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DEVICE_NATIVE_ENDIAN);
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R_MAX * 4 * t->nr_timers);
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sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
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sysbus_init_mmio_region(dev, &t->mmio);
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return 0;
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return 0;
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}
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}
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@ -49,6 +49,7 @@
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struct xlx_uartlite
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struct xlx_uartlite
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{
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{
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion mmio;
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CharDriverState *chr;
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CharDriverState *chr;
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qemu_irq irq;
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qemu_irq irq;
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@ -82,7 +83,8 @@ static void uart_update_status(struct xlx_uartlite *s)
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s->regs[R_STATUS] = r;
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s->regs[R_STATUS] = r;
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}
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}
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static uint32_t uart_readl (void *opaque, target_phys_addr_t addr)
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static uint64_t
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uart_read(void *opaque, target_phys_addr_t addr, unsigned int size)
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{
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{
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struct xlx_uartlite *s = opaque;
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struct xlx_uartlite *s = opaque;
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uint32_t r = 0;
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uint32_t r = 0;
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@ -107,9 +109,11 @@ static uint32_t uart_readl (void *opaque, target_phys_addr_t addr)
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}
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}
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static void
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static void
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uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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uart_write(void *opaque, target_phys_addr_t addr,
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uint64_t val64, unsigned int size)
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{
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{
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struct xlx_uartlite *s = opaque;
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struct xlx_uartlite *s = opaque;
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uint32_t value = val64;
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unsigned char ch = value;
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unsigned char ch = value;
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addr >>= 2;
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addr >>= 2;
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@ -147,16 +151,14 @@ uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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uart_update_irq(s);
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uart_update_irq(s);
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}
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}
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static CPUReadMemoryFunc * const uart_read[] = {
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static const MemoryRegionOps uart_ops = {
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&uart_readl,
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.read = uart_read,
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&uart_readl,
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.write = uart_write,
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&uart_readl,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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.valid = {
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.min_access_size = 1,
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static CPUWriteMemoryFunc * const uart_write[] = {
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.max_access_size = 4
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&uart_writel,
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}
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&uart_writel,
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&uart_writel,
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};
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};
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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@ -196,14 +198,12 @@ static void uart_event(void *opaque, int event)
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static int xilinx_uartlite_init(SysBusDevice *dev)
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static int xilinx_uartlite_init(SysBusDevice *dev)
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{
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{
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struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
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struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
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int uart_regs;
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(dev, &s->irq);
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uart_update_status(s);
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uart_update_status(s);
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uart_regs = cpu_register_io_memory(uart_read, uart_write, s,
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memory_region_init_io(&s->mmio, &uart_ops, s, "xilinx-uartlite", R_MAX * 4);
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio_region(dev, &s->mmio);
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sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
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s->chr = qdev_init_chardev(&dev->qdev);
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s->chr = qdev_init_chardev(&dev->qdev);
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if (s->chr)
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if (s->chr)
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