omap2: convert to memory API (part II)
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity
parent
9bac7d6c15
commit
011a98a15b
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@ -833,6 +833,8 @@ struct omap_mpu_state_s {
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MemoryRegion tap_iomem;
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MemoryRegion imif_ram;
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MemoryRegion emiff_ram;
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MemoryRegion sdram;
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MemoryRegion sram;
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struct omap_dma_port_if_s {
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uint32_t (*read[3])(struct omap_mpu_state_s *s,
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87
hw/omap2.c
87
hw/omap2.c
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@ -1000,6 +1000,8 @@ static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
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struct omap_prcm_s {
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qemu_irq irq[3];
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struct omap_mpu_state_s *mpu;
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MemoryRegion iomem0;
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MemoryRegion iomem1;
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uint32_t irqst[3];
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uint32_t irqen[3];
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@ -1038,11 +1040,16 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
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/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
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}
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static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
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static uint64_t omap_prcm_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
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uint32_t ret;
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if (size != 4) {
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return omap_badwidth_read32(opaque, addr);
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}
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switch (addr) {
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case 0x000: /* PRCM_REVISION */
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return 0x10;
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@ -1346,10 +1353,14 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
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}
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static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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uint64_t value, unsigned size)
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{
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struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
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if (size != 4) {
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return omap_badwidth_write32(opaque, addr, value);
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}
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switch (addr) {
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case 0x000: /* PRCM_REVISION */
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case 0x054: /* PRCM_VOLTST */
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@ -1699,16 +1710,10 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
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omap_badwidth_read32,
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omap_badwidth_read32,
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omap_prcm_read,
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};
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static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
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omap_badwidth_write32,
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omap_badwidth_write32,
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omap_prcm_write,
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static const MemoryRegionOps omap_prcm_ops = {
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.read = omap_prcm_read,
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.write = omap_prcm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void omap_prcm_reset(struct omap_prcm_s *s)
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@ -1795,7 +1800,6 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
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qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
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struct omap_mpu_state_s *mpu)
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{
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int iomemtype;
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struct omap_prcm_s *s = (struct omap_prcm_s *)
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g_malloc0(sizeof(struct omap_prcm_s));
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@ -1805,10 +1809,12 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
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s->mpu = mpu;
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omap_prcm_coldreset(s);
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iomemtype = cpu_register_io_memory(omap_prcm_readfn,
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omap_prcm_writefn, s, DEVICE_NATIVE_ENDIAN);
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omap_l4_attach(ta, 0, iomemtype);
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omap_l4_attach(ta, 1, iomemtype);
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memory_region_init_io(&s->iomem0, &omap_prcm_ops, s, "omap.pcrm0",
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omap_l4_region_size(ta, 0));
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memory_region_init_io(&s->iomem1, &omap_prcm_ops, s, "omap.pcrm1",
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omap_l4_region_size(ta, 1));
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omap_l4_attach_region(ta, 0, &s->iomem0);
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omap_l4_attach_region(ta, 1, &s->iomem1);
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return s;
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}
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@ -1816,6 +1822,7 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
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/* System and Pinout control */
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struct omap_sysctl_s {
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struct omap_mpu_state_s *mpu;
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MemoryRegion iomem;
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uint32_t sysconfig;
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uint32_t devconfig;
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@ -2069,16 +2076,20 @@ static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
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omap_sysctl_read8,
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omap_badwidth_read32, /* TODO */
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omap_sysctl_read,
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};
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static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
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omap_sysctl_write8,
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omap_badwidth_write32, /* TODO */
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omap_sysctl_write,
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static const MemoryRegionOps omap_sysctl_ops = {
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.old_mmio = {
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.read = {
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omap_sysctl_read8,
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omap_badwidth_read32, /* TODO */
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omap_sysctl_read,
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},
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.write = {
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omap_sysctl_write8,
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omap_badwidth_write32, /* TODO */
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omap_sysctl_write,
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},
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void omap_sysctl_reset(struct omap_sysctl_s *s)
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@ -2168,16 +2179,15 @@ static void omap_sysctl_reset(struct omap_sysctl_s *s)
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static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
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omap_clk iclk, struct omap_mpu_state_s *mpu)
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{
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int iomemtype;
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struct omap_sysctl_s *s = (struct omap_sysctl_s *)
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g_malloc0(sizeof(struct omap_sysctl_s));
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s->mpu = mpu;
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omap_sysctl_reset(s);
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iomemtype = cpu_register_io_memory(omap_sysctl_readfn,
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omap_sysctl_writefn, s, DEVICE_NATIVE_ENDIAN);
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omap_l4_attach(ta, 0, iomemtype);
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memory_region_init_io(&s->iomem, &omap_sysctl_ops, s, "omap.sysctl",
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omap_l4_region_size(ta, 0));
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omap_l4_attach_region(ta, 0, &s->iomem);
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return s;
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}
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@ -2236,7 +2246,6 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
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{
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struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
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g_malloc0(sizeof(struct omap_mpu_state_s));
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ram_addr_t sram_base, q2_base;
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qemu_irq *cpu_irq;
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qemu_irq dma_irqs[4];
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DriveInfo *dinfo;
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@ -2260,12 +2269,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
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omap_clk_init(s);
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/* Memory-mapped stuff */
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cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
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(q2_base = qemu_ram_alloc(NULL, "omap2.dram",
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s->sdram_size)) | IO_MEM_RAM);
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cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
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(sram_base = qemu_ram_alloc(NULL, "omap2.sram",
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s->sram_size)) | IO_MEM_RAM);
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memory_region_init_ram(&s->sdram, NULL, "omap2.dram", s->sdram_size);
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memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
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memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size);
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memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
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s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
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@ -2298,9 +2305,9 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
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s->port->addr_valid = omap2_validate_addr;
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/* Register SDRAM and SRAM ports for fast DMA transfers. */
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soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(q2_base),
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soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
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OMAP2_Q2_BASE, s->sdram_size);
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soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(sram_base),
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soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
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OMAP2_SRAM_BASE, s->sram_size);
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s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
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