target-ppc: Introduce DFP Encode BCD to DPD
Add emulation of the PowerPC Decimal Floating Point Encode Binary Coded Decimal to Densely Packed Decimal instructions denbcd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -1049,3 +1049,75 @@ void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b, uint32_t sp) \
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DFP_HELPER_DEDPD(ddedpd, 64)
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DFP_HELPER_DEDPD(ddedpdq, 128)
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static inline uint8_t dfp_get_bcd_digit_64(uint64_t *t, unsigned n)
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{
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return *t >> ((n << 2) & 63) & 15;
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}
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static inline uint8_t dfp_get_bcd_digit_128(uint64_t *t, unsigned n)
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{
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return t[(n & 0x10) ? HI_IDX : LO_IDX] >> ((n << 2) & 63) & 15;
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}
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#define DFP_HELPER_ENBCD(op, size) \
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void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b, uint32_t s) \
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{ \
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struct PPC_DFP dfp; \
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uint8_t digits[32]; \
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int n = 0, offset = 0, sgn = 0, nonzero = 0; \
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\
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dfp_prepare_decimal##size(&dfp, 0, b, env); \
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\
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decNumberZero(&dfp.t); \
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\
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if (s) { \
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uint8_t sgnNibble = dfp_get_bcd_digit_##size(dfp.b64, offset++); \
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switch (sgnNibble) { \
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case 0xD: \
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case 0xB: \
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sgn = 1; \
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break; \
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case 0xC: \
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case 0xF: \
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case 0xA: \
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case 0xE: \
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sgn = 0; \
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break; \
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default: \
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dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FPSCR_VE); \
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return; \
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} \
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} \
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\
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while (offset < (size)/4) { \
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n++; \
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digits[(size)/4-n] = dfp_get_bcd_digit_##size(dfp.b64, offset++); \
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if (digits[(size)/4-n] > 10) { \
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dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FPSCR_VE); \
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return; \
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} else { \
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nonzero |= (digits[(size)/4-n] > 0); \
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} \
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} \
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\
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if (nonzero) { \
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decNumberSetBCD(&dfp.t, digits+((size)/4)-n, n); \
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} \
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\
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if (s && sgn) { \
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dfp.t.bits |= DECNEG; \
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} \
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decimal##size##FromNumber((decimal##size *)dfp.t64, &dfp.t, \
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&dfp.context); \
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dfp_set_FPRF_from_FRT(&dfp); \
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if ((size) == 64) { \
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t[0] = dfp.t64[0]; \
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} else if ((size) == 128) { \
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t[0] = dfp.t64[HI_IDX]; \
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t[1] = dfp.t64[LO_IDX]; \
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} \
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}
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DFP_HELPER_ENBCD(denbcd, 64)
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DFP_HELPER_ENBCD(denbcdq, 128)
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@ -656,3 +656,5 @@ DEF_HELPER_3(dctfix, void, env, fprp, fprp)
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DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
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DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
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DEF_HELPER_4(ddedpdq, void, env, fprp, fprp, i32)
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DEF_HELPER_4(denbcd, void, env, fprp, fprp, i32)
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DEF_HELPER_4(denbcdq, void, env, fprp, fprp, i32)
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@ -8396,6 +8396,8 @@ GEN_DFP_T_B_Rc(dctfix)
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GEN_DFP_T_B_Rc(dctfixq)
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GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
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/*** SPE extension ***/
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/* Register moves */
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@ -11363,6 +11365,8 @@ GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
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GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
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GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
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GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
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GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
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GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
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#undef GEN_SPE
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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