target-ppc: convert POWER2 load/store instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -561,9 +561,6 @@ struct CPUPPCState {
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target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
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/* Floating point execution context */
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/* temporary float registers */
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float64 ft0;
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float64 ft1;
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float_status fp_status;
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/* floating point registers */
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float64 fpr[32];
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@ -45,9 +45,6 @@ register target_ulong T2 asm(AREG3);
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#define TDX "%016lx"
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#endif
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#define FT0 (env->ft0)
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#define FT1 (env->ft1)
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#if defined (DEBUG_OP)
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# define RETURN() __asm__ __volatile__("nop" : : : "memory");
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#else
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@ -309,48 +309,4 @@ void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
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T0 = i;
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}
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/* XXX: TAGs are not managed */
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void glue(do_POWER2_lfq, MEMSUFFIX) (void)
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{
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FT0 = glue(ldfq, MEMSUFFIX)((uint32_t)T0);
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FT1 = glue(ldfq, MEMSUFFIX)((uint32_t)(T0 + 4));
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}
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static always_inline float64 glue(ldfqr, MEMSUFFIX) (target_ulong EA)
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{
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CPU_DoubleU u;
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u.d = glue(ldfq, MEMSUFFIX)(EA);
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u.ll = bswap64(u.ll);
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return u.d;
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}
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void glue(do_POWER2_lfq_le, MEMSUFFIX) (void)
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{
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FT0 = glue(ldfqr, MEMSUFFIX)((uint32_t)(T0 + 4));
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FT1 = glue(ldfqr, MEMSUFFIX)((uint32_t)T0);
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}
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void glue(do_POWER2_stfq, MEMSUFFIX) (void)
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{
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glue(stfq, MEMSUFFIX)((uint32_t)T0, FT0);
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glue(stfq, MEMSUFFIX)((uint32_t)(T0 + 4), FT1);
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}
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static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, float64 d)
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{
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CPU_DoubleU u;
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u.d = d;
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u.ll = bswap64(u.ll);
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glue(stfq, MEMSUFFIX)(EA, u.d);
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}
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void glue(do_POWER2_stfq_le, MEMSUFFIX) (void)
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{
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glue(stfqr, MEMSUFFIX)((uint32_t)(T0 + 4), FT0);
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glue(stfqr, MEMSUFFIX)((uint32_t)T0, FT1);
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}
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#undef MEMSUFFIX
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@ -616,30 +616,4 @@ void OPPROTO glue(op_POWER_lscbx, MEMSUFFIX) (void)
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RETURN();
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}
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/* POWER2 quad load and store */
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/* XXX: TAGs are not managed */
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void OPPROTO glue(op_POWER2_lfq, MEMSUFFIX) (void)
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{
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glue(do_POWER2_lfq, MEMSUFFIX)();
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RETURN();
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}
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void glue(op_POWER2_lfq_le, MEMSUFFIX) (void)
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{
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glue(do_POWER2_lfq_le, MEMSUFFIX)();
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RETURN();
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}
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void OPPROTO glue(op_POWER2_stfq, MEMSUFFIX) (void)
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{
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glue(do_POWER2_stfq, MEMSUFFIX)();
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RETURN();
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}
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void OPPROTO glue(op_POWER2_stfq_le, MEMSUFFIX) (void)
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{
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glue(do_POWER2_stfq_le, MEMSUFFIX)();
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RETURN();
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}
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#undef MEMSUFFIX
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@ -71,7 +71,6 @@ static TCGv_i32 cpu_access_type;
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/* dyngen register indexes */
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static TCGv cpu_T[3];
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static TCGv_i64 cpu_FT[2];
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#include "gen-icount.h"
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@ -103,11 +102,6 @@ void ppc_translate_init(void)
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#endif
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#endif
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cpu_FT[0] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, ft0), "FT0");
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cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, ft1), "FT1");
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p = cpu_reg_names;
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for (i = 0; i < 8; i++) {
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@ -5102,134 +5096,121 @@ GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
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/* POWER2 specific instructions */
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/* Quad manipulation (load/store two floats at a time) */
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/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
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#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
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#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
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#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
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#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
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#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
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#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
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#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
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#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
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#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
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#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
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#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
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#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
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#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
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#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
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#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
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#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
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#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
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#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
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static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
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GEN_MEM_FUNCS(POWER2_lfq),
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};
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static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
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GEN_MEM_FUNCS(POWER2_stfq),
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};
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/* lfq */
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GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(cpu_T[0], ctx, 0);
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op_POWER2_lfq();
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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gen_addr_imm_index(t0, ctx, 0);
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gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t0, t0, 8);
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gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
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tcg_temp_free(t0);
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}
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/* lfqu */
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GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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{
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int ra = rA(ctx->opcode);
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(cpu_T[0], ctx, 0);
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op_POWER2_lfq();
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_addr_imm_index(t0, ctx, 0);
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gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t1, t0, 8);
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gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
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if (ra != 0)
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tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
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tcg_gen_mov_tl(cpu_gpr[ra], t0);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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/* lfqux */
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GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
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{
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int ra = rA(ctx->opcode);
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_reg_index(cpu_T[0], ctx);
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op_POWER2_lfq();
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_addr_reg_index(t0, ctx);
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gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t1, t0, 8);
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gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
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if (ra != 0)
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tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
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tcg_gen_mov_tl(cpu_gpr[ra], t0);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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/* lfqx */
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GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_reg_index(cpu_T[0], ctx);
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op_POWER2_lfq();
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
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tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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gen_addr_reg_index(t0, ctx);
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gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t0, t0, 8);
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gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
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tcg_temp_free(t0);
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}
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/* stfq */
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GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(cpu_T[0], ctx, 0);
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
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tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
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op_POWER2_stfq();
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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gen_addr_imm_index(t0, ctx, 0);
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gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t0, t0, 8);
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gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
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tcg_temp_free(t0);
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}
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/* stfqu */
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GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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{
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int ra = rA(ctx->opcode);
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(cpu_T[0], ctx, 0);
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
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tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
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op_POWER2_stfq();
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_addr_imm_index(t0, ctx, 0);
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gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t1, t0, 8);
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gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
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if (ra != 0)
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tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
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tcg_gen_mov_tl(cpu_gpr[ra], t0);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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/* stfqux */
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GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
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{
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int ra = rA(ctx->opcode);
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_reg_index(cpu_T[0], ctx);
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
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tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
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op_POWER2_stfq();
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_addr_reg_index(t0, ctx);
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gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t1, t0, 8);
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gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
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if (ra != 0)
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tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
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tcg_gen_mov_tl(cpu_gpr[ra], t0);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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/* stfqx */
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GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_reg_index(cpu_T[0], ctx);
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tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
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tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
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op_POWER2_stfq();
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int rd = rD(ctx->opcode);
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TCGv t0 = tcg_temp_new();
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gen_addr_reg_index(t0, ctx);
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gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
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tcg_gen_addi_tl(t0, t0, 8);
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gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
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tcg_temp_free(t0);
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}
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/* BookE specific instructions */
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