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target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* 

This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.

The ultimate goal is

 -- Non-secure regimes:
    ARMMMUIdx_E10_0,
    ARMMMUIdx_E20_0,
    ARMMMUIdx_E10_1,
    ARMMMUIdx_E2,
    ARMMMUIdx_E20_2,

 -- Secure regimes:
    ARMMMUIdx_SE10_0,
    ARMMMUIdx_SE10_1,
    ARMMMUIdx_SE3,

 -- Helper mmu_idx for non-secure EL1&0 stage1 and stage2
    ARMMMUIdx_Stage2,
    ARMMMUIdx_Stage1_E0,
    ARMMMUIdx_Stage1_E1,

The 'S' prefix is reserved for "Secure".  Unless otherwise specified,
each mmu_idx represents all stages of translation.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-07 14:04:22 +00:00 committed by Peter Maydell
parent 527db2be8b
commit 01b98b6864
5 changed files with 31 additions and 31 deletions
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8
target/arm/cpu.h
View File

@ -2905,8 +2905,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
#define ARM_MMU_IDX_COREIDX_MASK 0x7
typedef enum ARMMMUIdx {
ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
@ -2931,8 +2931,8 @@ typedef enum ARMMMUIdx {
* for use when calling tlb_flush_by_mmuidx() and friends.
*/
typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_S12NSE0 = 1 << 0,
ARMMMUIdxBit_S12NSE1 = 1 << 1,
ARMMMUIdxBit_E10_0 = 1 << 0,
ARMMMUIdxBit_E10_1 = 1 << 1,
ARMMMUIdxBit_S1E2 = 1 << 2,
ARMMMUIdxBit_S1E3 = 1 << 3,
ARMMMUIdxBit_S1SE0 = 1 << 4,

40
target/arm/helper.c
View File

@ -670,8 +670,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0 |
ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS);
}
@ -681,8 +681,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0 |
ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS);
}
@ -3117,7 +3117,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
if (arm_feature(env, ARM_FEATURE_EL2)) {
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
} else {
format64 |= arm_current_el(env) == 2;
@ -3216,11 +3216,11 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
break;
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
mmu_idx = ARMMMUIdx_S12NSE1;
mmu_idx = ARMMMUIdx_E10_1;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
mmu_idx = ARMMMUIdx_S12NSE0;
mmu_idx = ARMMMUIdx_E10_0;
break;
default:
g_assert_not_reached();
@ -3278,10 +3278,10 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
break;
case 4: /* AT S12E1R, AT S12E1W */
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1;
break;
case 6: /* AT S12E0R, AT S12E0W */
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0;
break;
default:
g_assert_not_reached();
@ -3581,8 +3581,8 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* Accesses to VTTBR may change the VMID so we must flush the TLB. */
if (raw_read(env, ri) != value) {
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0 |
ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS);
raw_write(env, ri, value);
}
@ -3943,7 +3943,7 @@ static int vae1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else {
return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
}
@ -3979,9 +3979,9 @@ static int alle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS;
} else {
return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
}
@ -8817,8 +8817,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
*/
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0);
}
return mmu_idx;
}
@ -8861,8 +8861,8 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
return true;
default:
return false;
case ARMMMUIdx_S12NSE0:
case ARMMMUIdx_S12NSE1:
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
g_assert_not_reached();
}
}
@ -10766,7 +10766,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
/* Call ourselves recursively to do the stage 1 and then stage 2
* translations.
*/
@ -11294,7 +11294,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
if (el < 2 && arm_is_secure_below_el3(env)) {
return ARMMMUIdx_S1SE0 + el;
} else {
return ARMMMUIdx_S12NSE0 + el;
return ARMMMUIdx_E10_0 + el;
}
}

4
target/arm/internals.h
View File

@ -808,8 +808,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_S12NSE0:
case ARMMMUIdx_S12NSE1:
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1:
case ARMMMUIdx_S1E2:

4
target/arm/translate-a64.c
View File

@ -113,8 +113,8 @@ static inline int get_a64_user_mem_index(DisasContext *s)
ARMMMUIdx useridx;
switch (s->mmu_idx) {
case ARMMMUIdx_S12NSE1:
useridx = ARMMMUIdx_S12NSE0;
case ARMMMUIdx_E10_1:
useridx = ARMMMUIdx_E10_0;
break;
case ARMMMUIdx_S1SE1:
useridx = ARMMMUIdx_S1SE0;

6
target/arm/translate.c
View File

@ -153,9 +153,9 @@ static inline int get_a32_user_mem_index(DisasContext *s)
*/
switch (s->mmu_idx) {
case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
case ARMMMUIdx_S12NSE0:
case ARMMMUIdx_S12NSE1:
return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0);
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
case ARMMMUIdx_S1E3:
case ARMMMUIdx_S1SE0:
case ARMMMUIdx_S1SE1: