x86: Debug register emulation (Jan Kiszka)
Built on top of previously enhanced breakpoint/watchpoint support, this patch adds full debug register emulation for the x86 architecture. Many corner cases were considered, and the result was successfully tested inside a Linux guest with gdb, but I won't be surprised if one or two scenarios still behave differently in reality. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5747 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori
parent
2dc9f4117c
commit
01df040b52
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@ -403,7 +403,7 @@ void cpu_loop(CPUX86State *env)
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queue_signal(env, info.si_signo, &info);
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}
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break;
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case EXCP01_SSTP:
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case EXCP01_DB:
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case EXCP03_INT3:
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#ifndef TARGET_X86_64
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if (env->eflags & VM_MASK) {
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@ -413,7 +413,7 @@ void cpu_loop(CPUX86State *env)
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{
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info.si_signo = SIGTRAP;
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info.si_errno = 0;
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if (trapnr == EXCP01_SSTP) {
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if (trapnr == EXCP01_DB) {
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info.si_code = TARGET_TRAP_BRKPT;
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info._sifields._sigfault._addr = env->eip;
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} else {
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@ -205,6 +205,16 @@
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#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
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#define CR4_OSXMMEXCPT_MASK (1 << 10)
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#define DR6_BD (1 << 13)
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#define DR6_BS (1 << 14)
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#define DR6_BT (1 << 15)
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#define DR6_FIXED_1 0xffff0ff0
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#define DR7_GD (1 << 13)
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#define DR7_TYPE_SHIFT 16
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#define DR7_LEN_SHIFT 18
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#define DR7_FIXED_1 0x00000400
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#define PG_PRESENT_BIT 0
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#define PG_RW_BIT 1
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#define PG_USER_BIT 2
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@ -362,7 +372,7 @@
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#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */
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#define EXCP00_DIVZ 0
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#define EXCP01_SSTP 1
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#define EXCP01_DB 1
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#define EXCP02_NMI 2
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#define EXCP03_INT3 3
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#define EXCP04_INTO 4
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@ -596,6 +606,10 @@ typedef struct CPUX86State {
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int exception_is_int;
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target_ulong exception_next_eip;
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target_ulong dr[8]; /* debug registers */
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union {
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CPUBreakpoint *cpu_breakpoint[4];
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CPUWatchpoint *cpu_watchpoint[4];
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}; /* break/watchpoints for dr[0..3] */
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uint32_t smbase;
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int old_exception; /* exception in flight */
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@ -789,6 +803,26 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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}
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#endif
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static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
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{
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return (dr7 >> (index * 2)) & 3;
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}
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static inline int hw_breakpoint_type(unsigned long dr7, int index)
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{
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return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3;
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}
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static inline int hw_breakpoint_len(unsigned long dr7, int index)
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{
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int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3);
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return (len == 2) ? 8 : len + 1;
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}
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void hw_breakpoint_insert(CPUState *env, int index);
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void hw_breakpoint_remove(CPUState *env, int index);
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int check_hw_breakpoints(CPUState *env, int force_dr6_update);
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#include "cpu-all.h"
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#include "exec-all.h"
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@ -34,8 +34,6 @@
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//#define DEBUG_MMU
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static int cpu_x86_register (CPUX86State *env, const char *cpu_model);
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static void add_flagname_to_bitmaps(char *flagname, uint32_t *features,
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uint32_t *ext_features,
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uint32_t *ext2_features,
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@ -93,35 +91,6 @@ static void add_flagname_to_bitmaps(char *flagname, uint32_t *features,
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fprintf(stderr, "CPU feature %s not found\n", flagname);
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}
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CPUX86State *cpu_x86_init(const char *cpu_model)
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{
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CPUX86State *env;
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static int inited;
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env = qemu_mallocz(sizeof(CPUX86State));
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if (!env)
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return NULL;
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cpu_exec_init(env);
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env->cpu_model_str = cpu_model;
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/* init various static tables */
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if (!inited) {
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inited = 1;
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optimize_flags_init();
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}
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if (cpu_x86_register(env, cpu_model) < 0) {
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cpu_x86_close(env);
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return NULL;
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}
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cpu_reset(env);
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#ifdef USE_KQEMU
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kqemu_init(env);
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#endif
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if (kvm_enabled())
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kvm_init_vcpu(env);
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return env;
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}
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typedef struct x86_def_t {
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const char *name;
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uint32_t level;
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@ -499,6 +468,12 @@ void cpu_reset(CPUX86State *env)
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env->fpuc = 0x37f;
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env->mxcsr = 0x1f80;
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memset(env->dr, 0, sizeof(env->dr));
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env->dr[6] = DR6_FIXED_1;
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env->dr[7] = DR7_FIXED_1;
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cpu_breakpoint_remove_all(env, BP_CPU);
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cpu_watchpoint_remove_all(env, BP_CPU);
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}
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void cpu_x86_close(CPUX86State *env)
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@ -1295,6 +1270,105 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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paddr = (pte & TARGET_PAGE_MASK) + page_offset;
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return paddr;
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}
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void hw_breakpoint_insert(CPUState *env, int index)
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{
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int type, err = 0;
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switch (hw_breakpoint_type(env->dr[7], index)) {
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case 0:
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if (hw_breakpoint_enabled(env->dr[7], index))
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err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU,
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&env->cpu_breakpoint[index]);
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break;
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case 1:
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type = BP_CPU | BP_MEM_WRITE;
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goto insert_wp;
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case 2:
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/* No support for I/O watchpoints yet */
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break;
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case 3:
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type = BP_CPU | BP_MEM_ACCESS;
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insert_wp:
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err = cpu_watchpoint_insert(env, env->dr[index],
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hw_breakpoint_len(env->dr[7], index),
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type, &env->cpu_watchpoint[index]);
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break;
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}
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if (err)
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env->cpu_breakpoint[index] = NULL;
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}
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void hw_breakpoint_remove(CPUState *env, int index)
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{
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if (!env->cpu_breakpoint[index])
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return;
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switch (hw_breakpoint_type(env->dr[7], index)) {
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case 0:
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if (hw_breakpoint_enabled(env->dr[7], index))
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cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]);
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break;
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case 1:
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case 3:
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cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]);
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break;
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case 2:
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/* No support for I/O watchpoints yet */
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break;
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}
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}
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int check_hw_breakpoints(CPUState *env, int force_dr6_update)
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{
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target_ulong dr6;
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int reg, type;
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int hit_enabled = 0;
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dr6 = env->dr[6] & ~0xf;
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for (reg = 0; reg < 4; reg++) {
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type = hw_breakpoint_type(env->dr[7], reg);
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if ((type == 0 && env->dr[reg] == env->eip) ||
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((type & 1) && env->cpu_watchpoint[reg] &&
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(env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT))) {
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dr6 |= 1 << reg;
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if (hw_breakpoint_enabled(env->dr[7], reg))
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hit_enabled = 1;
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}
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}
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if (hit_enabled || force_dr6_update)
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env->dr[6] = dr6;
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return hit_enabled;
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}
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static CPUDebugExcpHandler *prev_debug_excp_handler;
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void raise_exception(int exception_index);
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static void breakpoint_handler(CPUState *env)
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{
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CPUBreakpoint *bp;
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if (env->watchpoint_hit) {
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if (env->watchpoint_hit->flags & BP_CPU) {
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env->watchpoint_hit = NULL;
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if (check_hw_breakpoints(env, 0))
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raise_exception(EXCP01_DB);
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else
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cpu_resume_from_signal(env, NULL);
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}
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} else {
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for (bp = env->breakpoints; bp != NULL; bp = bp->next)
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if (bp->pc == env->eip) {
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if (bp->flags & BP_CPU) {
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check_hw_breakpoints(env, 1);
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raise_exception(EXCP01_DB);
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}
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break;
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}
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}
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if (prev_debug_excp_handler)
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prev_debug_excp_handler(env);
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}
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#endif /* !CONFIG_USER_ONLY */
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static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
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@ -1532,3 +1606,36 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
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break;
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}
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}
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CPUX86State *cpu_x86_init(const char *cpu_model)
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{
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CPUX86State *env;
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static int inited;
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env = qemu_mallocz(sizeof(CPUX86State));
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if (!env)
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return NULL;
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cpu_exec_init(env);
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env->cpu_model_str = cpu_model;
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/* init various static tables */
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if (!inited) {
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inited = 1;
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optimize_flags_init();
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#ifndef CONFIG_USER_ONLY
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prev_debug_excp_handler =
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cpu_set_debug_excp_handler(breakpoint_handler);
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#endif
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}
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if (cpu_x86_register(env, cpu_model) < 0) {
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cpu_x86_close(env);
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return NULL;
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}
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cpu_reset(env);
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#ifdef USE_KQEMU
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kqemu_init(env);
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#endif
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if (kvm_enabled())
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kvm_init_vcpu(env);
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return env;
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}
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@ -259,6 +259,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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for(i = 0; i < 8; i++)
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qemu_get_betls(f, &env->dr[i]);
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cpu_breakpoint_remove_all(env, BP_CPU);
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cpu_watchpoint_remove_all(env, BP_CPU);
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for (i = 0; i < 4; i++)
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hw_breakpoint_insert(env, i);
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/* MMU */
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qemu_get_sbe32s(f, &a20_mask);
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@ -496,6 +496,17 @@ static void switch_tss(int tss_selector,
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/* XXX: different exception if CALL ? */
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raise_exception_err(EXCP0D_GPF, 0);
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}
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#ifndef CONFIG_USER_ONLY
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/* reset local breakpoints */
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if (env->dr[7] & 0x55) {
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for (i = 0; i < 4; i++) {
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if (hw_breakpoint_enabled(env->dr[7], i) == 0x1)
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hw_breakpoint_remove(env, i);
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}
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env->dr[7] &= ~0x55;
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}
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#endif
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}
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/* check if Port I/O is allowed in TSS */
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@ -1879,8 +1890,11 @@ void helper_cmpxchg16b(target_ulong a0)
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void helper_single_step(void)
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{
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env->dr[6] |= 0x4000;
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raise_exception(EXCP01_SSTP);
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#ifndef CONFIG_USER_ONLY
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check_hw_breakpoints(env, 1);
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env->dr[6] |= DR6_BS;
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#endif
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raise_exception(EXCP01_DB);
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}
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void helper_cpuid(void)
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@ -2868,6 +2882,10 @@ target_ulong helper_read_crN(int reg)
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void helper_write_crN(int reg, target_ulong t0)
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{
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}
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void helper_movl_drN_T0(int reg, target_ulong t0)
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{
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}
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#else
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target_ulong helper_read_crN(int reg)
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{
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@ -2913,6 +2931,24 @@ void helper_write_crN(int reg, target_ulong t0)
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break;
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}
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}
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void helper_movl_drN_T0(int reg, target_ulong t0)
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{
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int i;
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if (reg < 4) {
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hw_breakpoint_remove(env, reg);
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env->dr[reg] = t0;
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hw_breakpoint_insert(env, reg);
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} else if (reg == 7) {
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for (i = 0; i < 4; i++)
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hw_breakpoint_remove(env, i);
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env->dr[7] = t0;
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for (i = 0; i < 4; i++)
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hw_breakpoint_insert(env, i);
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} else
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env->dr[reg] = t0;
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}
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#endif
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void helper_lmsw(target_ulong t0)
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@ -2929,12 +2965,6 @@ void helper_clts(void)
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env->hflags &= ~HF_TS_MASK;
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}
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/* XXX: do more */
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void helper_movl_drN_T0(int reg, target_ulong t0)
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{
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env->dr[reg] = t0;
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}
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void helper_invlpg(target_ulong addr)
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{
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helper_svm_check_intercept_param(SVM_EXIT_INVLPG, 0);
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