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target-alpha: convert cmp* instructions to TCG

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5249 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-09-18 09:24:25 +00:00
parent adf3c8b6e9
commit 01ff9cc8fe
2 changed files with 37 additions and 50 deletions
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45
target-alpha/op.c
View File

@ -208,51 +208,6 @@ void OPPROTO op_umulh (void)
} }
/* Tests */ /* Tests */
void OPPROTO op_cmpult (void)
{
if (T0 < T1)
T0 = 1;
else
T0 = 0;
RETURN();
}
void OPPROTO op_cmpule (void)
{
if (T0 <= T1)
T0 = 1;
else
T0 = 0;
RETURN();
}
void OPPROTO op_cmpeq (void)
{
if (T0 == T1)
T0 = 1;
else
T0 = 0;
RETURN();
}
void OPPROTO op_cmplt (void)
{
if ((int64_t)T0 < (int64_t)T1)
T0 = 1;
else
T0 = 0;
RETURN();
}
void OPPROTO op_cmple (void)
{
if ((int64_t)T0 <= (int64_t)T1)
T0 = 1;
else
T0 = 0;
RETURN();
}
void OPPROTO op_cmpbge (void) void OPPROTO op_cmpbge (void)
{ {
helper_cmpbge(); helper_cmpbge();

42
target-alpha/translate.c
View File

@ -561,6 +561,38 @@ static always_inline void gen_byte_manipulation(void *helper,
tcg_gen_movi_i64(cpu_ir[rc], 0); tcg_gen_movi_i64(cpu_ir[rc], 0);
} }
static always_inline void gen_cmp(TCGCond cond,
int ra, int rb, int rc,
int islit, int8_t lit)
{
int l1, l2;
TCGv tmp;
if (unlikely(rc == 31))
return;
l1 = gen_new_label();
l2 = gen_new_label();
if (ra != 31) {
tmp = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_mov_i64(tmp, cpu_ir[ra]);
} else
tmp = tcg_const_i64(0);
if (islit)
tcg_gen_brcondi_i64(cond, tmp, lit, l1);
else if (rb != 31)
tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);
else
tcg_gen_brcondi_i64(cond, tmp, 0, l1);
tcg_gen_movi_i64(cpu_ir[rc], 0);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_movi_i64(cpu_ir[rc], 1);
gen_set_label(l2);
}
static always_inline int translate_one (DisasContext *ctx, uint32_t insn) static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
{ {
uint32_t palcode; uint32_t palcode;
@ -848,7 +880,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x1D: case 0x1D:
/* CMPULT */ /* CMPULT */
gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit); gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
break; break;
case 0x20: case 0x20:
/* ADDQ */ /* ADDQ */
@ -940,7 +972,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x2D: case 0x2D:
/* CMPEQ */ /* CMPEQ */
gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit); gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
break; break;
case 0x32: case 0x32:
/* S8ADDQ */ /* S8ADDQ */
@ -992,7 +1024,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x3D: case 0x3D:
/* CMPULE */ /* CMPULE */
gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit); gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
break; break;
case 0x40: case 0x40:
/* ADDL/V */ /* ADDL/V */
@ -1004,7 +1036,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x4D: case 0x4D:
/* CMPLT */ /* CMPLT */
gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit); gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
break; break;
case 0x60: case 0x60:
/* ADDQ/V */ /* ADDQ/V */
@ -1016,7 +1048,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x6D: case 0x6D:
/* CMPLE */ /* CMPLE */
gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit); gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
break; break;
default: default:
goto invalid_opc; goto invalid_opc;