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Ignore PR flag in FPSCR when performing fmov, by Magnus Damm.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3005 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-06-22 11:47:05 +00:00
parent e67888a7da
commit 022a22c7e1
1 changed files with 7 additions and 38 deletions
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45
target-sh4/translate.c
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@ -648,10 +648,7 @@ void decode_opc(DisasContext * ctx)
gen_op_xor_T0_rN(REG(B11_8)); gen_op_xor_T0_rN(REG(B11_8));
return; return;
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) { if (ctx->fpscr & FPSCR_SZ) {
gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_fmov_DT0_drN(XREG(B11_8));
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0110) if (ctx->opcode & 0x0110)
break; /* illegal instruction */ break; /* illegal instruction */
gen_op_fmov_drN_DT0(DREG(B7_4)); gen_op_fmov_drN_DT0(DREG(B7_4));
@ -662,11 +659,7 @@ void decode_opc(DisasContext * ctx)
} }
return; return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) { if (ctx->fpscr & FPSCR_SZ) {
gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010) if (ctx->opcode & 0x0010)
break; /* illegal instruction */ break; /* illegal instruction */
gen_op_fmov_drN_DT0(DREG(B7_4)); gen_op_fmov_drN_DT0(DREG(B7_4));
@ -679,11 +672,7 @@ void decode_opc(DisasContext * ctx)
} }
return; return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) { if (ctx->fpscr & FPSCR_SZ) {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
gen_op_fmov_DT0_drN(XREG(B11_8));
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100) if (ctx->opcode & 0x0100)
break; /* illegal instruction */ break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4)); gen_op_movl_rN_T0(REG(B7_4));
@ -696,12 +685,7 @@ void decode_opc(DisasContext * ctx)
} }
return; return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) { if (ctx->fpscr & FPSCR_SZ) {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
gen_op_fmov_DT0_drN(XREG(B11_8));
gen_op_inc8_rN(REG(B7_4));
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100) if (ctx->opcode & 0x0100)
break; /* illegal instruction */ break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4)); gen_op_movl_rN_T0(REG(B7_4));
@ -716,12 +700,7 @@ void decode_opc(DisasContext * ctx)
} }
return; return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) { if (ctx->fpscr & FPSCR_SZ) {
gen_op_dec8_rN(REG(B11_8));
gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100) if (ctx->opcode & 0x0100)
break; /* illegal instruction */ break; /* illegal instruction */
gen_op_dec8_rN(REG(B11_8)); gen_op_dec8_rN(REG(B11_8));
@ -736,12 +715,7 @@ void decode_opc(DisasContext * ctx)
} }
return; return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) { if (ctx->fpscr & FPSCR_SZ) {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldfq_T0_DT0(ctx);
gen_op_fmov_DT0_drN(XREG(B11_8));
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100) if (ctx->opcode & 0x0100)
break; /* illegal instruction */ break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4)); gen_op_movl_rN_T0(REG(B7_4));
@ -756,12 +730,7 @@ void decode_opc(DisasContext * ctx)
} }
return; return;
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) { if (ctx->fpscr & FPSCR_SZ) {
gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stfq_DT0_T1(ctx);
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010) if (ctx->opcode & 0x0010)
break; /* illegal instruction */ break; /* illegal instruction */
gen_op_fmov_drN_DT0(DREG(B7_4)); gen_op_fmov_drN_DT0(DREG(B7_4));