From 023c3a9707d0d9259a1e858cdf7804dd10973fca Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 11 Dec 2014 19:08:14 +0100 Subject: [PATCH] serial: update LSR on enabling/disabling FIFOs When the transmit FIFO is emptied or enabled, the transmitter hold register is empty. When it is disabled, it is also emptied and in addition the previous contents of the transmitter hold register are discarded. In either case, the THRE bit in LSR must be set and THRI raised. When the receive FIFO is emptied or enabled, the data ready and break bits must be cleared in LSR. Likewise when the receive FIFO is disabled. Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Paolo Bonzini --- hw/char/serial.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/char/serial.c b/hw/char/serial.c index 9adb12667d..76054a542a 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -377,12 +377,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, /* FIFO clear */ if (val & UART_FCR_RFR) { + s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); timer_del(s->fifo_timeout_timer); s->timeout_ipending = 0; fifo8_reset(&s->recv_fifo); } if (val & UART_FCR_XFR) { + s->lsr |= UART_LSR_THRE; + s->thr_ipending = 1; fifo8_reset(&s->xmit_fifo); }