target/ppc: cpu_init: Move Timebase registration into the common function
Now that the 601 was removed, all of our CPUs have a timebase, so that can be moved into the common function. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Fabiano Rosas
Cédric Le Goater
parent
e78280a237
commit
024b40e0ae
@ -221,6 +221,24 @@ static void register_generic_sprs(PowerPCCPU *cpu)
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pcc->svr);
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}
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}
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/* Time base */
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spr_register(env, SPR_VTBL, "TBL",
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&spr_read_tbl, SPR_NOACCESS,
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&spr_read_tbl, SPR_NOACCESS,
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0x00000000);
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spr_register(env, SPR_TBL, "TBL",
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&spr_read_tbl, SPR_NOACCESS,
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&spr_read_tbl, &spr_write_tbl,
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0x00000000);
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spr_register(env, SPR_VTBU, "TBU",
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&spr_read_tbu, SPR_NOACCESS,
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&spr_read_tbu, SPR_NOACCESS,
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0x00000000);
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spr_register(env, SPR_TBU, "TBU",
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&spr_read_tbu, SPR_NOACCESS,
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&spr_read_tbu, &spr_write_tbu,
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0x00000000);
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}
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/* SPR common to all non-embedded PowerPC, including 601 */
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@ -409,27 +427,6 @@ static void register_high_BATs(CPUPPCState *env)
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#endif
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}
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/* Generic PowerPC time base */
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static void register_tbl(CPUPPCState *env)
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{
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spr_register(env, SPR_VTBL, "TBL",
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&spr_read_tbl, SPR_NOACCESS,
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&spr_read_tbl, SPR_NOACCESS,
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0x00000000);
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spr_register(env, SPR_TBL, "TBL",
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&spr_read_tbl, SPR_NOACCESS,
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&spr_read_tbl, &spr_write_tbl,
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0x00000000);
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spr_register(env, SPR_VTBU, "TBU",
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&spr_read_tbu, SPR_NOACCESS,
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&spr_read_tbu, SPR_NOACCESS,
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0x00000000);
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spr_register(env, SPR_TBU, "TBU",
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&spr_read_tbu, SPR_NOACCESS,
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&spr_read_tbu, &spr_write_tbu,
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0x00000000);
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}
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/* Softare table search registers */
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static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
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{
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@ -2319,8 +2316,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
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static void init_proc_405(CPUPPCState *env)
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{
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/* Time base */
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register_tbl(env);
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register_40x_sprs(env);
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register_405_sprs(env);
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/* Bus access control */
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@ -2386,8 +2381,6 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
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static void init_proc_440EP(CPUPPCState *env)
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{
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/* Time base */
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register_tbl(env);
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register_BookE_sprs(env, 0x000000000000FFFFULL);
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register_440_sprs(env);
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register_usprgh_sprs(env);
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@ -2528,8 +2521,6 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
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static void init_proc_440GP(CPUPPCState *env)
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{
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/* Time base */
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register_tbl(env);
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register_BookE_sprs(env, 0x000000000000FFFFULL);
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register_440_sprs(env);
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register_usprgh_sprs(env);
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@ -2611,8 +2602,6 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
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static void init_proc_440x5(CPUPPCState *env)
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{
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/* Time base */
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register_tbl(env);
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register_BookE_sprs(env, 0x000000000000FFFFULL);
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register_440_sprs(env);
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register_usprgh_sprs(env);
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@ -2750,8 +2739,6 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
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static void init_proc_MPC5xx(CPUPPCState *env)
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{
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/* Time base */
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register_tbl(env);
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register_5xx_8xx_sprs(env);
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register_5xx_sprs(env);
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init_excp_MPC5xx(env);
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@ -2794,8 +2781,6 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
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static void init_proc_MPC8xx(CPUPPCState *env)
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{
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/* Time base */
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register_tbl(env);
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register_5xx_8xx_sprs(env);
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register_8xx_sprs(env);
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init_excp_MPC8xx(env);
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@ -2843,8 +2828,6 @@ static void init_proc_G2(CPUPPCState *env)
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register_sdr1_sprs(env);
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register_G2_755_sprs(env);
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register_G2_sprs(env);
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/* Time base */
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register_tbl(env);
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/* External access control */
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spr_register(env, SPR_EAR, "EAR",
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SPR_NOACCESS, SPR_NOACCESS,
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@ -2956,8 +2939,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
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static void init_proc_e200(CPUPPCState *env)
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{
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/* Time base */
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register_tbl(env);
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register_BookE_sprs(env, 0x000000070000FFFFULL);
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spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
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@ -3114,8 +3095,6 @@ static void init_proc_e300(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_603_sprs(env);
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/* Time base */
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register_tbl(env);
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/* hardware implementation registers */
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spr_register(env, SPR_HID0, "HID0",
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SPR_NOACCESS, SPR_NOACCESS,
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@ -3229,8 +3208,6 @@ static void init_proc_e500(CPUPPCState *env, int version)
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int i;
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#endif
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/* Time base */
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register_tbl(env);
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/*
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* XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
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* complain when accessing them.
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@ -3674,8 +3651,6 @@ static void init_proc_603(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_603_sprs(env);
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/* Time base */
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register_tbl(env);
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/* hardware implementation registers */
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spr_register(env, SPR_HID0, "HID0",
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SPR_NOACCESS, SPR_NOACCESS,
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@ -3779,8 +3754,6 @@ static void init_proc_604(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_604_sprs(env);
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/* Time base */
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register_tbl(env);
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/* Hardware implementation registers */
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spr_register(env, SPR_HID0, "HID0",
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SPR_NOACCESS, SPR_NOACCESS,
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@ -3854,8 +3827,6 @@ static void init_proc_604E(CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Time base */
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register_tbl(env);
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/* Hardware implementation registers */
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spr_register(env, SPR_HID0, "HID0",
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SPR_NOACCESS, SPR_NOACCESS,
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@ -3919,8 +3890,6 @@ static void init_proc_740(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* Thermal management */
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register_thrm_sprs(env);
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/* Hardware implementation registers */
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@ -3991,8 +3960,6 @@ static void init_proc_750(CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, spr_access_nop,
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0x00000000);
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/* Time base */
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register_tbl(env);
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/* Thermal management */
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register_thrm_sprs(env);
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/* Hardware implementation registers */
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@ -4067,8 +4034,6 @@ static void init_proc_750cl(CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, spr_access_nop,
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0x00000000);
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/* Time base */
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register_tbl(env);
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/* Thermal management */
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/* Those registers are fake on 750CL */
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spr_register(env, SPR_THRM1, "THRM1",
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@ -4264,8 +4229,6 @@ static void init_proc_750cx(CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, spr_access_nop,
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0x00000000);
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/* Time base */
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register_tbl(env);
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/* Thermal management */
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register_thrm_sprs(env);
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@ -4343,8 +4306,6 @@ static void init_proc_750fx(CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, spr_access_nop,
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0x00000000);
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/* Time base */
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register_tbl(env);
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/* Thermal management */
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register_thrm_sprs(env);
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@ -4427,8 +4388,6 @@ static void init_proc_750gx(CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, spr_access_nop,
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0x00000000);
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/* Time base */
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register_tbl(env);
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/* Thermal management */
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register_thrm_sprs(env);
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@ -4507,8 +4466,6 @@ static void init_proc_745(CPUPPCState *env)
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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register_G2_755_sprs(env);
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/* Time base */
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register_tbl(env);
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/* Thermal management */
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register_thrm_sprs(env);
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/* Hardware implementation registers */
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@ -4582,8 +4539,6 @@ static void init_proc_755(CPUPPCState *env)
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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register_G2_755_sprs(env);
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/* Time base */
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register_tbl(env);
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/* L2 cache control */
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spr_register(env, SPR_L2CR, "L2CR",
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SPR_NOACCESS, SPR_NOACCESS,
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@ -4666,8 +4621,6 @@ static void init_proc_7400(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -4742,8 +4695,6 @@ static void init_proc_7410(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -4825,8 +4776,6 @@ static void init_proc_7440(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -4929,8 +4878,6 @@ static void init_proc_7450(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -5055,8 +5002,6 @@ static void init_proc_7445(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -5188,8 +5133,6 @@ static void init_proc_7455(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -5323,8 +5266,6 @@ static void init_proc_7457(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -5478,8 +5419,6 @@ static void init_proc_e600(CPUPPCState *env)
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register_ne_601_sprs(env);
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register_sdr1_sprs(env);
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register_7xx_sprs(env);
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/* Time base */
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register_tbl(env);
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/* 74xx specific SPR */
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register_74xx_sprs(env);
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vscr_init(env, 0x00010000);
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@ -6303,7 +6242,6 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
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static void init_proc_book3s_common(CPUPPCState *env)
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{
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register_ne_601_sprs(env);
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register_tbl(env);
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register_usprg3_sprs(env);
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register_book3s_altivec_sprs(env);
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register_book3s_pmu_sup_sprs(env);
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