target/arm: Reorg do_coproc_insn
Move the ri == NULL case to the top of the function and return. This allows the else to be removed and the code unindented. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230106194451.1213153-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
b3aa2f2128
commit
0371fa90a1
@ -4715,220 +4715,220 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
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bool isread, int rt, int rt2)
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{
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const ARMCPRegInfo *ri;
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bool need_exit_tb;
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ri = get_arm_cp_reginfo(s->cp_regs,
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ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
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if (ri) {
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bool need_exit_tb;
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/* Check access permissions */
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if (!cp_access_ok(s->current_el, ri, isread)) {
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unallocated_encoding(s);
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return;
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}
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if (s->hstr_active || ri->accessfn ||
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(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
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/* Emit code to perform further access permissions checks at
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* runtime; this may result in an exception.
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* Note that on XScale all cp0..c13 registers do an access check
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* call in order to handle c15_cpar.
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*/
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uint32_t syndrome;
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/* Note that since we are an implementation which takes an
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* exception on a trapped conditional instruction only if the
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* instruction passes its condition code check, we can take
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* advantage of the clause in the ARM ARM that allows us to set
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* the COND field in the instruction to 0xE in all cases.
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* We could fish the actual condition out of the insn (ARM)
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* or the condexec bits (Thumb) but it isn't necessary.
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*/
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switch (cpnum) {
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case 14:
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if (is64) {
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syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
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isread, false);
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} else {
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syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
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rt, isread, false);
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}
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break;
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case 15:
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if (is64) {
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syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
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isread, false);
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} else {
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syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
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rt, isread, false);
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}
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break;
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default:
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/* ARMv8 defines that only coprocessors 14 and 15 exist,
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* so this can only happen if this is an ARMv7 or earlier CPU,
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* in which case the syndrome information won't actually be
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* guest visible.
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*/
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assert(!arm_dc_feature(s, ARM_FEATURE_V8));
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syndrome = syn_uncategorized();
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break;
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}
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gen_set_condexec(s);
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gen_update_pc(s, 0);
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gen_helper_access_check_cp_reg(cpu_env,
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tcg_constant_ptr(ri),
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tcg_constant_i32(syndrome),
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tcg_constant_i32(isread));
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} else if (ri->type & ARM_CP_RAISES_EXC) {
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/*
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* The readfn or writefn might raise an exception;
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* synchronize the CPU state in case it does.
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*/
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gen_set_condexec(s);
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gen_update_pc(s, 0);
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}
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/* Handle special cases first */
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switch (ri->type & ARM_CP_SPECIAL_MASK) {
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case 0:
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break;
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case ARM_CP_NOP:
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return;
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case ARM_CP_WFI:
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if (isread) {
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unallocated_encoding(s);
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return;
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}
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gen_update_pc(s, curr_insn_len(s));
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s->base.is_jmp = DISAS_WFI;
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return;
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default:
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g_assert_not_reached();
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}
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if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
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gen_io_start();
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}
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if (isread) {
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/* Read */
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if (is64) {
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TCGv_i64 tmp64;
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TCGv_i32 tmp;
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if (ri->type & ARM_CP_CONST) {
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tmp64 = tcg_constant_i64(ri->resetvalue);
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} else if (ri->readfn) {
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tmp64 = tcg_temp_new_i64();
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gen_helper_get_cp_reg64(tmp64, cpu_env,
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tcg_constant_ptr(ri));
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} else {
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tmp64 = tcg_temp_new_i64();
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tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
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}
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tmp = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(tmp, tmp64);
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store_reg(s, rt, tmp);
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tmp = tcg_temp_new_i32();
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tcg_gen_extrh_i64_i32(tmp, tmp64);
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tcg_temp_free_i64(tmp64);
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store_reg(s, rt2, tmp);
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} else {
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TCGv_i32 tmp;
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if (ri->type & ARM_CP_CONST) {
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tmp = tcg_constant_i32(ri->resetvalue);
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} else if (ri->readfn) {
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tmp = tcg_temp_new_i32();
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gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
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} else {
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tmp = load_cpu_offset(ri->fieldoffset);
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}
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if (rt == 15) {
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/* Destination register of r15 for 32 bit loads sets
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* the condition codes from the high 4 bits of the value
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*/
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gen_set_nzcv(tmp);
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tcg_temp_free_i32(tmp);
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} else {
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store_reg(s, rt, tmp);
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}
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}
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if (!ri) {
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/*
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* Unknown register; this might be a guest error or a QEMU
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* unimplemented feature.
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*/
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if (is64) {
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qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
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"64 bit system register cp:%d opc1: %d crm:%d "
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"(%s)\n",
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isread ? "read" : "write", cpnum, opc1, crm,
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s->ns ? "non-secure" : "secure");
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} else {
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/* Write */
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if (ri->type & ARM_CP_CONST) {
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/* If not forbidden by access permissions, treat as WI */
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return;
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}
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if (is64) {
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TCGv_i32 tmplo, tmphi;
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TCGv_i64 tmp64 = tcg_temp_new_i64();
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tmplo = load_reg(s, rt);
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tmphi = load_reg(s, rt2);
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tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi);
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tcg_temp_free_i32(tmplo);
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tcg_temp_free_i32(tmphi);
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if (ri->writefn) {
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gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
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tmp64);
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} else {
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tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
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}
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tcg_temp_free_i64(tmp64);
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} else {
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TCGv_i32 tmp = load_reg(s, rt);
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if (ri->writefn) {
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gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
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tcg_temp_free_i32(tmp);
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} else {
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store_cpu_offset(tmp, ri->fieldoffset, 4);
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}
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}
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qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
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"system register cp:%d opc1:%d crn:%d crm:%d "
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"opc2:%d (%s)\n",
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isread ? "read" : "write", cpnum, opc1, crn,
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crm, opc2, s->ns ? "non-secure" : "secure");
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}
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/* I/O operations must end the TB here (whether read or write) */
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need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) &&
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(ri->type & ARM_CP_IO));
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if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
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/*
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* A write to any coprocessor register that ends a TB
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* must rebuild the hflags for the next TB.
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*/
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gen_rebuild_hflags(s, ri->type & ARM_CP_NEWEL);
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/*
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* We default to ending the TB on a coprocessor register write,
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* but allow this to be suppressed by the register definition
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* (usually only necessary to work around guest bugs).
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*/
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need_exit_tb = true;
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}
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if (need_exit_tb) {
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gen_lookup_tb(s);
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}
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unallocated_encoding(s);
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return;
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}
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/* Unknown register; this might be a guest error or a QEMU
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* unimplemented feature.
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*/
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if (is64) {
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qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
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"64 bit system register cp:%d opc1: %d crm:%d "
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"(%s)\n",
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isread ? "read" : "write", cpnum, opc1, crm,
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s->ns ? "non-secure" : "secure");
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} else {
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qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
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"system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
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"(%s)\n",
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isread ? "read" : "write", cpnum, opc1, crn, crm, opc2,
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s->ns ? "non-secure" : "secure");
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/* Check access permissions */
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if (!cp_access_ok(s->current_el, ri, isread)) {
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unallocated_encoding(s);
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return;
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}
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unallocated_encoding(s);
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return;
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if (s->hstr_active || ri->accessfn ||
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(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
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/*
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* Emit code to perform further access permissions checks at
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* runtime; this may result in an exception.
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* Note that on XScale all cp0..c13 registers do an access check
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* call in order to handle c15_cpar.
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*/
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uint32_t syndrome;
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/*
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* Note that since we are an implementation which takes an
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* exception on a trapped conditional instruction only if the
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* instruction passes its condition code check, we can take
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* advantage of the clause in the ARM ARM that allows us to set
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* the COND field in the instruction to 0xE in all cases.
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* We could fish the actual condition out of the insn (ARM)
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* or the condexec bits (Thumb) but it isn't necessary.
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*/
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switch (cpnum) {
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case 14:
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if (is64) {
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syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
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isread, false);
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} else {
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syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
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rt, isread, false);
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}
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break;
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case 15:
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if (is64) {
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syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
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isread, false);
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} else {
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syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
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rt, isread, false);
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}
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break;
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default:
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/*
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* ARMv8 defines that only coprocessors 14 and 15 exist,
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* so this can only happen if this is an ARMv7 or earlier CPU,
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* in which case the syndrome information won't actually be
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* guest visible.
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*/
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assert(!arm_dc_feature(s, ARM_FEATURE_V8));
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syndrome = syn_uncategorized();
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break;
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}
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gen_set_condexec(s);
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gen_update_pc(s, 0);
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gen_helper_access_check_cp_reg(cpu_env,
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tcg_constant_ptr(ri),
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tcg_constant_i32(syndrome),
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tcg_constant_i32(isread));
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} else if (ri->type & ARM_CP_RAISES_EXC) {
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/*
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* The readfn or writefn might raise an exception;
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* synchronize the CPU state in case it does.
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*/
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gen_set_condexec(s);
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gen_update_pc(s, 0);
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}
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/* Handle special cases first */
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switch (ri->type & ARM_CP_SPECIAL_MASK) {
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case 0:
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break;
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case ARM_CP_NOP:
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return;
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case ARM_CP_WFI:
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if (isread) {
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unallocated_encoding(s);
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return;
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}
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gen_update_pc(s, curr_insn_len(s));
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s->base.is_jmp = DISAS_WFI;
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return;
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default:
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g_assert_not_reached();
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}
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if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
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gen_io_start();
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}
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if (isread) {
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/* Read */
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if (is64) {
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TCGv_i64 tmp64;
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TCGv_i32 tmp;
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if (ri->type & ARM_CP_CONST) {
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tmp64 = tcg_constant_i64(ri->resetvalue);
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} else if (ri->readfn) {
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tmp64 = tcg_temp_new_i64();
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gen_helper_get_cp_reg64(tmp64, cpu_env,
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tcg_constant_ptr(ri));
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} else {
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tmp64 = tcg_temp_new_i64();
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tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
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}
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tmp = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(tmp, tmp64);
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store_reg(s, rt, tmp);
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tmp = tcg_temp_new_i32();
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tcg_gen_extrh_i64_i32(tmp, tmp64);
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tcg_temp_free_i64(tmp64);
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store_reg(s, rt2, tmp);
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} else {
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TCGv_i32 tmp;
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if (ri->type & ARM_CP_CONST) {
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tmp = tcg_constant_i32(ri->resetvalue);
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} else if (ri->readfn) {
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tmp = tcg_temp_new_i32();
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gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
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} else {
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tmp = load_cpu_offset(ri->fieldoffset);
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}
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if (rt == 15) {
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/* Destination register of r15 for 32 bit loads sets
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* the condition codes from the high 4 bits of the value
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*/
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gen_set_nzcv(tmp);
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tcg_temp_free_i32(tmp);
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} else {
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store_reg(s, rt, tmp);
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}
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}
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} else {
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/* Write */
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if (ri->type & ARM_CP_CONST) {
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/* If not forbidden by access permissions, treat as WI */
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return;
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}
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if (is64) {
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TCGv_i32 tmplo, tmphi;
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TCGv_i64 tmp64 = tcg_temp_new_i64();
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tmplo = load_reg(s, rt);
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tmphi = load_reg(s, rt2);
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tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi);
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tcg_temp_free_i32(tmplo);
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tcg_temp_free_i32(tmphi);
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if (ri->writefn) {
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gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tmp64);
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} else {
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tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
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}
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tcg_temp_free_i64(tmp64);
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} else {
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TCGv_i32 tmp = load_reg(s, rt);
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if (ri->writefn) {
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gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
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tcg_temp_free_i32(tmp);
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} else {
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store_cpu_offset(tmp, ri->fieldoffset, 4);
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}
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}
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}
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/* I/O operations must end the TB here (whether read or write) */
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need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) &&
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(ri->type & ARM_CP_IO));
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if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
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/*
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* A write to any coprocessor register that ends a TB
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* must rebuild the hflags for the next TB.
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*/
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gen_rebuild_hflags(s, ri->type & ARM_CP_NEWEL);
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/*
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* We default to ending the TB on a coprocessor register write,
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* but allow this to be suppressed by the register definition
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* (usually only necessary to work around guest bugs).
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*/
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need_exit_tb = true;
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}
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if (need_exit_tb) {
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gen_lookup_tb(s);
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}
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}
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/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */
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