target/arm: Fix checkpatch space errors in helper.c
Fix the following: ERROR: spaces required around that '|' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '+' (ctx:VxB) ERROR: space prohibited between function name and open parenthesis '(' (the last two still have some occurrences in macros which I left behind because it might impact readability) Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20221213190537.511-3-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -205,7 +205,7 @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
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uint32_t regidx = (uintptr_t)key;
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uint32_t regidx = (uintptr_t)key;
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const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
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if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
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cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
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cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
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/* The value array need not be initialized at this point */
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/* The value array need not be initialized at this point */
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cpu->cpreg_array_len++;
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cpu->cpreg_array_len++;
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@ -219,7 +219,7 @@ static void count_cpreg(gpointer key, gpointer opaque)
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ri = g_hash_table_lookup(cpu->cp_regs, key);
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ri = g_hash_table_lookup(cpu->cp_regs, key);
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if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
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if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
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cpu->cpreg_array_len++;
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cpu->cpreg_array_len++;
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}
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}
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}
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}
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@ -2350,11 +2350,11 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
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.resetfn = arm_cp_reset_ignore },
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.resetfn = arm_cp_reset_ignore },
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{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
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{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
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.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
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.access = PL0_R|PL1_W,
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.access = PL0_R | PL1_W,
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.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
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.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
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.resetvalue = 0},
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.resetvalue = 0},
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{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
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{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
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.access = PL0_R|PL1_W,
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.access = PL0_R | PL1_W,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
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offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
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offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
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.resetfn = arm_cp_reset_ignore },
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.resetfn = arm_cp_reset_ignore },
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@ -4315,17 +4315,17 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
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.resetvalue = 0 },
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.resetvalue = 0 },
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/* The cache ops themselves: these all NOP for QEMU */
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/* The cache ops themselves: these all NOP for QEMU */
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{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
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{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
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.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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.access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
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{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
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{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
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.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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.access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
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{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
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{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
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.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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.access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
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{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
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{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
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.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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.access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
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{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
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{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
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.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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.access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
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{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
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{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
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.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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.access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
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};
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};
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static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
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static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
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@ -8695,7 +8695,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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ARMCPRegInfo cbar = {
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ARMCPRegInfo cbar = {
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.name = "CBAR",
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.name = "CBAR",
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.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
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.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
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.access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
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.access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
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.fieldoffset = offsetof(CPUARMState,
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.fieldoffset = offsetof(CPUARMState,
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cp15.c15_config_base_address)
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cp15.c15_config_base_address)
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};
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};
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@ -9673,11 +9673,11 @@ static void switch_mode(CPUARMState *env, int mode)
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return;
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return;
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if (old_mode == ARM_CPU_MODE_FIQ) {
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if (old_mode == ARM_CPU_MODE_FIQ) {
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memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
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memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
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memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
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memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
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} else if (mode == ARM_CPU_MODE_FIQ) {
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} else if (mode == ARM_CPU_MODE_FIQ) {
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memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
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memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
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memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
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memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
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}
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}
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i = bank_number(old_mode);
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i = bank_number(old_mode);
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@ -11181,7 +11181,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
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RESULT(sum, n, 16); \
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RESULT(sum, n, 16); \
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if (sum >= 0) \
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if (sum >= 0) \
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ge |= 3 << (n * 2); \
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ge |= 3 << (n * 2); \
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} while(0)
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} while (0)
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#define SARITH8(a, b, n, op) do { \
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#define SARITH8(a, b, n, op) do { \
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int32_t sum; \
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int32_t sum; \
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@ -11189,7 +11189,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
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RESULT(sum, n, 8); \
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RESULT(sum, n, 8); \
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if (sum >= 0) \
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if (sum >= 0) \
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ge |= 1 << n; \
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ge |= 1 << n; \
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} while(0)
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} while (0)
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#define ADD16(a, b, n) SARITH16(a, b, n, +)
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#define ADD16(a, b, n) SARITH16(a, b, n, +)
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@ -11208,7 +11208,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
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RESULT(sum, n, 16); \
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RESULT(sum, n, 16); \
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if ((sum >> 16) == 1) \
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if ((sum >> 16) == 1) \
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ge |= 3 << (n * 2); \
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ge |= 3 << (n * 2); \
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} while(0)
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} while (0)
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#define ADD8(a, b, n) do { \
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#define ADD8(a, b, n) do { \
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uint32_t sum; \
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uint32_t sum; \
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@ -11216,7 +11216,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
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RESULT(sum, n, 8); \
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RESULT(sum, n, 8); \
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if ((sum >> 8) == 1) \
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if ((sum >> 8) == 1) \
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ge |= 1 << n; \
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ge |= 1 << n; \
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} while(0)
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} while (0)
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#define SUB16(a, b, n) do { \
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#define SUB16(a, b, n) do { \
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uint32_t sum; \
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uint32_t sum; \
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@ -11224,7 +11224,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
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RESULT(sum, n, 16); \
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RESULT(sum, n, 16); \
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if ((sum >> 16) == 0) \
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if ((sum >> 16) == 0) \
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ge |= 3 << (n * 2); \
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ge |= 3 << (n * 2); \
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} while(0)
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} while (0)
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#define SUB8(a, b, n) do { \
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#define SUB8(a, b, n) do { \
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uint32_t sum; \
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uint32_t sum; \
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@ -11232,7 +11232,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
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RESULT(sum, n, 8); \
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RESULT(sum, n, 8); \
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if ((sum >> 8) == 0) \
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if ((sum >> 8) == 0) \
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ge |= 1 << n; \
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ge |= 1 << n; \
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} while(0)
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} while (0)
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#define PFX u
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#define PFX u
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#define ARITH_GE
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#define ARITH_GE
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