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target/arm: Fix checkpatch space errors in helper.c 

Fix the following:

ERROR: spaces required around that '|' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '+' (ctx:VxB)
ERROR: space prohibited between function name and open parenthesis '('

(the last two still have some occurrences in macros which I left
behind because it might impact readability)

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Fabiano Rosas 2022-12-13 16:05:33 -03:00 committed by Peter Maydell
parent 9b37a28c78
commit 04215eb100
1 changed files with 21 additions and 21 deletions
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42
target/arm/helper.c
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@ -205,7 +205,7 @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
uint32_t regidx = (uintptr_t)key; uint32_t regidx = (uintptr_t)key;
const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
/* The value array need not be initialized at this point */ /* The value array need not be initialized at this point */
cpu->cpreg_array_len++; cpu->cpreg_array_len++;
@ -219,7 +219,7 @@ static void count_cpreg(gpointer key, gpointer opaque)
ri = g_hash_table_lookup(cpu->cp_regs, key); ri = g_hash_table_lookup(cpu->cp_regs, key);
if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
cpu->cpreg_array_len++; cpu->cpreg_array_len++;
} }
} }
@ -2350,11 +2350,11 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
.resetfn = arm_cp_reset_ignore }, .resetfn = arm_cp_reset_ignore },
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
.access = PL0_R|PL1_W, .access = PL0_R | PL1_W,
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
.resetvalue = 0}, .resetvalue = 0},
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
.access = PL0_R|PL1_W, .access = PL0_R | PL1_W,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
.resetfn = arm_cp_reset_ignore }, .resetfn = arm_cp_reset_ignore },
@ -4315,17 +4315,17 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
.resetvalue = 0 }, .resetvalue = 0 },
/* The cache ops themselves: these all NOP for QEMU */ /* The cache ops themselves: these all NOP for QEMU */
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
}; };
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@ -8695,7 +8695,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo cbar = { ARMCPRegInfo cbar = {
.name = "CBAR", .name = "CBAR",
.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
.access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
.fieldoffset = offsetof(CPUARMState, .fieldoffset = offsetof(CPUARMState,
cp15.c15_config_base_address) cp15.c15_config_base_address)
}; };
@ -9673,11 +9673,11 @@ static void switch_mode(CPUARMState *env, int mode)
return; return;
if (old_mode == ARM_CPU_MODE_FIQ) { if (old_mode == ARM_CPU_MODE_FIQ) {
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
} else if (mode == ARM_CPU_MODE_FIQ) { } else if (mode == ARM_CPU_MODE_FIQ) {
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
} }
i = bank_number(old_mode); i = bank_number(old_mode);
@ -11181,7 +11181,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 16); \ RESULT(sum, n, 16); \
if (sum >= 0) \ if (sum >= 0) \
ge |= 3 << (n * 2); \ ge |= 3 << (n * 2); \
} while(0) } while (0)
#define SARITH8(a, b, n, op) do { \ #define SARITH8(a, b, n, op) do { \
int32_t sum; \ int32_t sum; \
@ -11189,7 +11189,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 8); \ RESULT(sum, n, 8); \
if (sum >= 0) \ if (sum >= 0) \
ge |= 1 << n; \ ge |= 1 << n; \
} while(0) } while (0)
#define ADD16(a, b, n) SARITH16(a, b, n, +) #define ADD16(a, b, n) SARITH16(a, b, n, +)
@ -11208,7 +11208,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 16); \ RESULT(sum, n, 16); \
if ((sum >> 16) == 1) \ if ((sum >> 16) == 1) \
ge |= 3 << (n * 2); \ ge |= 3 << (n * 2); \
} while(0) } while (0)
#define ADD8(a, b, n) do { \ #define ADD8(a, b, n) do { \
uint32_t sum; \ uint32_t sum; \
@ -11216,7 +11216,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 8); \ RESULT(sum, n, 8); \
if ((sum >> 8) == 1) \ if ((sum >> 8) == 1) \
ge |= 1 << n; \ ge |= 1 << n; \
} while(0) } while (0)
#define SUB16(a, b, n) do { \ #define SUB16(a, b, n) do { \
uint32_t sum; \ uint32_t sum; \
@ -11224,7 +11224,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 16); \ RESULT(sum, n, 16); \
if ((sum >> 16) == 0) \ if ((sum >> 16) == 0) \
ge |= 3 << (n * 2); \ ge |= 3 << (n * 2); \
} while(0) } while (0)
#define SUB8(a, b, n) do { \ #define SUB8(a, b, n) do { \
uint32_t sum; \ uint32_t sum; \
@ -11232,7 +11232,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
RESULT(sum, n, 8); \ RESULT(sum, n, 8); \
if ((sum >> 8) == 0) \ if ((sum >> 8) == 0) \
ge |= 1 << n; \ ge |= 1 << n; \
} while(0) } while (0)
#define PFX u #define PFX u
#define ARITH_GE #define ARITH_GE