From 042374c92e83da5c8f906b9b97814a21eac2a09f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 23 Jul 2018 19:03:37 +0100 Subject: [PATCH] hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQ In icc_dir_write() we were incorrectly checking HCR_EL2.FMO when determining whether IRQ should be routed to EL2; this should be HCR_EL2.IMO (compare the GICv3 pseudocode ICC_DIR_EL1[]). Use the correct mask. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180723180337.17378-1-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 5c89be1af0..2a60568d82 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1550,7 +1550,7 @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, * tested in cases where we know !IsSecure is true. */ route_fiq_to_el2 = env->cp15.hcr_el2 & HCR_FMO; - route_irq_to_el2 = env->cp15.hcr_el2 & HCR_FMO; + route_irq_to_el2 = env->cp15.hcr_el2 & HCR_IMO; switch (arm_current_el(env)) { case 3: