target/arm: Rearrange cpu64.c so all the CPU initfns are together
cpu64.c has ended up in a slightly odd order -- it starts with the initfns for most of the models-real-hardware CPUs; after that comes a bunch of support code for SVE, SME, pauth and LPA2 properties. Then come the initfns for the 'host' and 'max' CPU types, and then after that one more models-real-hardware CPU initfn, for a64fx. (This ordering is partly historical and partly required because a64fx needs the SVE properties.) Reorder the file into: * CPU property support functions * initfns for real hardware CPUs * initfns for host and max * class boilerplate Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell
parent
f190bd1da1
commit
042e85d14c
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@ -116,313 +116,6 @@ static void aarch64_a35_initfn(Object *obj)
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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}
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static void aarch64_a57_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a57";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->isar.id_pfr0 = 0x00000131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->isar.id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->isar.dbgdidr = 0x3516d000;
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cpu->isar.dbgdevid = 0x01110f13;
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cpu->isar.dbgdevid1 = 0x2;
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cpu->isar.reset_pmcr_el0 = 0x41013000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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}
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static void aarch64_a53_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a53";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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cpu->midr = 0x410fd034;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x84448004; /* L1Ip = VIPT */
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cpu->reset_sctlr = 0x00c50838;
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cpu->isar.id_pfr0 = 0x00000131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->isar.id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
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cpu->isar.dbgdidr = 0x3516d000;
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cpu->isar.dbgdevid = 0x00110f13;
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cpu->isar.dbgdevid1 = 0x1;
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cpu->isar.reset_pmcr_el0 = 0x41033000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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}
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static void aarch64_a72_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a72";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->midr = 0x410fd083;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034080;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->isar.id_pfr0 = 0x00000131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->isar.id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->isar.dbgdidr = 0x3516d000;
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cpu->isar.dbgdevid = 0x01110f13;
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cpu->isar.dbgdevid1 = 0x2;
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cpu->isar.reset_pmcr_el0 = 0x41023000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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}
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static void aarch64_a76_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a76";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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/* Ordered by B2.4 AArch64 registers by functional group */
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cpu->clidr = 0x82000023;
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cpu->ctr = 0x8444C004;
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cpu->dcz_blocksize = 4;
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cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
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cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
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cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
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cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
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cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
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cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
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cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
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cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_dfr0 = 0x04010088;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00010142;
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cpu->isar.id_isar5 = 0x01011121;
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cpu->isar.id_isar6 = 0x00000010;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02122211;
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cpu->isar.id_mmfr4 = 0x00021110;
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cpu->isar.id_pfr0 = 0x10010131;
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cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
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cpu->isar.id_pfr2 = 0x00000011;
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cpu->midr = 0x414fd0b1; /* r4p1 */
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cpu->revidr = 0;
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/* From B2.18 CCSIDR_EL1 */
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cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
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cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
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/* From B2.93 SCTLR_EL3 */
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cpu->reset_sctlr = 0x30c50838;
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/* From B4.23 ICH_VTR_EL2 */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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/* From B5.1 AdvSIMD AArch64 register summary */
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x13211111;
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cpu->isar.mvfr2 = 0x00000043;
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/* From D5.1 AArch64 PMU register summary */
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cpu->isar.reset_pmcr_el0 = 0x410b3000;
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}
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static void aarch64_neoverse_n1_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,neoverse-n1";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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/* Ordered by B2.4 AArch64 registers by functional group */
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cpu->clidr = 0x82000023;
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cpu->ctr = 0x8444c004;
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cpu->dcz_blocksize = 4;
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cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
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cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
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cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
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cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
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cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
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cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
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cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
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cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_dfr0 = 0x04010088;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00010142;
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cpu->isar.id_isar5 = 0x01011121;
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cpu->isar.id_isar6 = 0x00000010;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02122211;
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cpu->isar.id_mmfr4 = 0x00021110;
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cpu->isar.id_pfr0 = 0x10010131;
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cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
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cpu->isar.id_pfr2 = 0x00000011;
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cpu->midr = 0x414fd0c1; /* r4p1 */
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cpu->revidr = 0;
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/* From B2.23 CCSIDR_EL1 */
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cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
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/* From B2.98 SCTLR_EL3 */
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cpu->reset_sctlr = 0x30c50838;
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/* From B4.23 ICH_VTR_EL2 */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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/* From B5.1 AdvSIMD AArch64 register summary */
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x13211111;
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cpu->isar.mvfr2 = 0x00000043;
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/* From D5.1 AArch64 PMU register summary */
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cpu->isar.reset_pmcr_el0 = 0x410c3000;
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}
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void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
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{
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/*
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@ -985,6 +678,362 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
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cpu->isar.id_aa64mmfr0 = t;
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}
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static void aarch64_a57_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a57";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->isar.id_pfr0 = 0x00000131;
|
||||
cpu->isar.id_pfr1 = 0x00011011;
|
||||
cpu->isar.id_dfr0 = 0x03010066;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x10101105;
|
||||
cpu->isar.id_mmfr1 = 0x40000000;
|
||||
cpu->isar.id_mmfr2 = 0x01260000;
|
||||
cpu->isar.id_mmfr3 = 0x02102211;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_isar6 = 0;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_aa64dfr0 = 0x10305106;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64mmfr0 = 0x00001124;
|
||||
cpu->isar.dbgdidr = 0x3516d000;
|
||||
cpu->isar.dbgdevid = 0x01110f13;
|
||||
cpu->isar.dbgdevid1 = 0x2;
|
||||
cpu->isar.reset_pmcr_el0 = 0x41013000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
|
||||
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
|
||||
cpu->dcz_blocksize = 4; /* 64 bytes */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
cpu->gic_pribits = 5;
|
||||
define_cortex_a72_a57_a53_cp_reginfo(cpu);
|
||||
}
|
||||
|
||||
static void aarch64_a53_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
cpu->dtb_compatible = "arm,cortex-a53";
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
||||
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
||||
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
||||
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
||||
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
||||
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
|
||||
cpu->midr = 0x410fd034;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034070;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->isar.id_pfr0 = 0x00000131;
|
||||
cpu->isar.id_pfr1 = 0x00011011;
|
||||
cpu->isar.id_dfr0 = 0x03010066;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x10101105;
|
||||
cpu->isar.id_mmfr1 = 0x40000000;
|
||||
cpu->isar.id_mmfr2 = 0x01260000;
|
||||
cpu->isar.id_mmfr3 = 0x02102211;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_isar6 = 0;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_aa64dfr0 = 0x10305106;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
|
||||
cpu->isar.dbgdidr = 0x3516d000;
|
||||
cpu->isar.dbgdevid = 0x00110f13;
|
||||
cpu->isar.dbgdevid1 = 0x1;
|
||||
cpu->isar.reset_pmcr_el0 = 0x41033000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
|
||||
cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
|
||||
cpu->dcz_blocksize = 4; /* 64 bytes */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
cpu->gic_pribits = 5;
|
||||
define_cortex_a72_a57_a53_cp_reginfo(cpu);
|
||||
}
|
||||
|
||||
static void aarch64_a72_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
cpu->dtb_compatible = "arm,cortex-a72";
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
||||
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
||||
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
||||
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
||||
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
||||
cpu->midr = 0x410fd083;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034080;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->isar.id_pfr0 = 0x00000131;
|
||||
cpu->isar.id_pfr1 = 0x00011011;
|
||||
cpu->isar.id_dfr0 = 0x03010066;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x10201105;
|
||||
cpu->isar.id_mmfr1 = 0x40000000;
|
||||
cpu->isar.id_mmfr2 = 0x01260000;
|
||||
cpu->isar.id_mmfr3 = 0x02102211;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_aa64dfr0 = 0x10305106;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64mmfr0 = 0x00001124;
|
||||
cpu->isar.dbgdidr = 0x3516d000;
|
||||
cpu->isar.dbgdevid = 0x01110f13;
|
||||
cpu->isar.dbgdevid1 = 0x2;
|
||||
cpu->isar.reset_pmcr_el0 = 0x41023000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
|
||||
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
|
||||
cpu->dcz_blocksize = 4; /* 64 bytes */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
cpu->gic_pribits = 5;
|
||||
define_cortex_a72_a57_a53_cp_reginfo(cpu);
|
||||
}
|
||||
|
||||
static void aarch64_a76_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
cpu->dtb_compatible = "arm,cortex-a76";
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
||||
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
||||
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
||||
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
||||
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
||||
|
||||
/* Ordered by B2.4 AArch64 registers by functional group */
|
||||
cpu->clidr = 0x82000023;
|
||||
cpu->ctr = 0x8444C004;
|
||||
cpu->dcz_blocksize = 4;
|
||||
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
|
||||
cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
|
||||
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
|
||||
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
|
||||
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
|
||||
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
|
||||
cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
|
||||
cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_dfr0 = 0x04010088;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00010142;
|
||||
cpu->isar.id_isar5 = 0x01011121;
|
||||
cpu->isar.id_isar6 = 0x00000010;
|
||||
cpu->isar.id_mmfr0 = 0x10201105;
|
||||
cpu->isar.id_mmfr1 = 0x40000000;
|
||||
cpu->isar.id_mmfr2 = 0x01260000;
|
||||
cpu->isar.id_mmfr3 = 0x02122211;
|
||||
cpu->isar.id_mmfr4 = 0x00021110;
|
||||
cpu->isar.id_pfr0 = 0x10010131;
|
||||
cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
|
||||
cpu->isar.id_pfr2 = 0x00000011;
|
||||
cpu->midr = 0x414fd0b1; /* r4p1 */
|
||||
cpu->revidr = 0;
|
||||
|
||||
/* From B2.18 CCSIDR_EL1 */
|
||||
cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
|
||||
cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
|
||||
|
||||
/* From B2.93 SCTLR_EL3 */
|
||||
cpu->reset_sctlr = 0x30c50838;
|
||||
|
||||
/* From B4.23 ICH_VTR_EL2 */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
cpu->gic_pribits = 5;
|
||||
|
||||
/* From B5.1 AdvSIMD AArch64 register summary */
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x13211111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
|
||||
/* From D5.1 AArch64 PMU register summary */
|
||||
cpu->isar.reset_pmcr_el0 = 0x410b3000;
|
||||
}
|
||||
|
||||
static void aarch64_a64fx_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
cpu->dtb_compatible = "arm,a64fx";
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
||||
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
||||
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
||||
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
||||
cpu->midr = 0x461f0010;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->ctr = 0x86668006;
|
||||
cpu->reset_sctlr = 0x30000180;
|
||||
cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
|
||||
cpu->isar.id_aa64pfr1 = 0x0000000000000000;
|
||||
cpu->isar.id_aa64dfr0 = 0x0000000010305408;
|
||||
cpu->isar.id_aa64dfr1 = 0x0000000000000000;
|
||||
cpu->id_aa64afr0 = 0x0000000000000000;
|
||||
cpu->id_aa64afr1 = 0x0000000000000000;
|
||||
cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
|
||||
cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
|
||||
cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
|
||||
cpu->isar.id_aa64isar0 = 0x0000000010211120;
|
||||
cpu->isar.id_aa64isar1 = 0x0000000000010001;
|
||||
cpu->isar.id_aa64zfr0 = 0x0000000000000000;
|
||||
cpu->clidr = 0x0000000080000023;
|
||||
cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
|
||||
cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
|
||||
cpu->dcz_blocksize = 6; /* 256 bytes */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
cpu->gic_pribits = 5;
|
||||
|
||||
/* The A64FX supports only 128, 256 and 512 bit vector lengths */
|
||||
aarch64_add_sve_properties(obj);
|
||||
cpu->sve_vq.supported = (1 << 0) /* 128bit */
|
||||
| (1 << 1) /* 256bit */
|
||||
| (1 << 3); /* 512bit */
|
||||
|
||||
cpu->isar.reset_pmcr_el0 = 0x46014040;
|
||||
|
||||
/* TODO: Add A64FX specific HPC extension registers */
|
||||
}
|
||||
|
||||
static void aarch64_neoverse_n1_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
cpu->dtb_compatible = "arm,neoverse-n1";
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
||||
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
||||
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
||||
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
||||
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
||||
|
||||
/* Ordered by B2.4 AArch64 registers by functional group */
|
||||
cpu->clidr = 0x82000023;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->dcz_blocksize = 4;
|
||||
cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
|
||||
cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
|
||||
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
|
||||
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
|
||||
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
|
||||
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
|
||||
cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
|
||||
cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_dfr0 = 0x04010088;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00010142;
|
||||
cpu->isar.id_isar5 = 0x01011121;
|
||||
cpu->isar.id_isar6 = 0x00000010;
|
||||
cpu->isar.id_mmfr0 = 0x10201105;
|
||||
cpu->isar.id_mmfr1 = 0x40000000;
|
||||
cpu->isar.id_mmfr2 = 0x01260000;
|
||||
cpu->isar.id_mmfr3 = 0x02122211;
|
||||
cpu->isar.id_mmfr4 = 0x00021110;
|
||||
cpu->isar.id_pfr0 = 0x10010131;
|
||||
cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
|
||||
cpu->isar.id_pfr2 = 0x00000011;
|
||||
cpu->midr = 0x414fd0c1; /* r4p1 */
|
||||
cpu->revidr = 0;
|
||||
|
||||
/* From B2.23 CCSIDR_EL1 */
|
||||
cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
|
||||
cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
|
||||
|
||||
/* From B2.98 SCTLR_EL3 */
|
||||
cpu->reset_sctlr = 0x30c50838;
|
||||
|
||||
/* From B4.23 ICH_VTR_EL2 */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
cpu->gic_pribits = 5;
|
||||
|
||||
/* From B5.1 AdvSIMD AArch64 register summary */
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x13211111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
|
||||
/* From D5.1 AArch64 PMU register summary */
|
||||
cpu->isar.reset_pmcr_el0 = 0x410c3000;
|
||||
}
|
||||
|
||||
static void aarch64_host_initfn(Object *obj)
|
||||
{
|
||||
#if defined(CONFIG_KVM)
|
||||
|
|
@ -1188,55 +1237,6 @@ static void aarch64_max_initfn(Object *obj)
|
|||
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
|
||||
}
|
||||
|
||||
static void aarch64_a64fx_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
cpu->dtb_compatible = "arm,a64fx";
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
||||
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
||||
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
||||
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
||||
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
||||
cpu->midr = 0x461f0010;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->ctr = 0x86668006;
|
||||
cpu->reset_sctlr = 0x30000180;
|
||||
cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
|
||||
cpu->isar.id_aa64pfr1 = 0x0000000000000000;
|
||||
cpu->isar.id_aa64dfr0 = 0x0000000010305408;
|
||||
cpu->isar.id_aa64dfr1 = 0x0000000000000000;
|
||||
cpu->id_aa64afr0 = 0x0000000000000000;
|
||||
cpu->id_aa64afr1 = 0x0000000000000000;
|
||||
cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
|
||||
cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
|
||||
cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
|
||||
cpu->isar.id_aa64isar0 = 0x0000000010211120;
|
||||
cpu->isar.id_aa64isar1 = 0x0000000000010001;
|
||||
cpu->isar.id_aa64zfr0 = 0x0000000000000000;
|
||||
cpu->clidr = 0x0000000080000023;
|
||||
cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
|
||||
cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
|
||||
cpu->dcz_blocksize = 6; /* 256 bytes */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
cpu->gic_pribits = 5;
|
||||
|
||||
/* The A64FX supports only 128, 256 and 512 bit vector lengths */
|
||||
aarch64_add_sve_properties(obj);
|
||||
cpu->sve_vq.supported = (1 << 0) /* 128bit */
|
||||
| (1 << 1) /* 256bit */
|
||||
| (1 << 3); /* 512bit */
|
||||
|
||||
cpu->isar.reset_pmcr_el0 = 0x46014040;
|
||||
|
||||
/* TODO: Add A64FX specific HPC extension registers */
|
||||
}
|
||||
|
||||
static const ARMCPUInfo aarch64_cpus[] = {
|
||||
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
|
||||
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
|
||||
|
|
|
|||
Loading…
Reference in New Issue