target-ppc: Disentangle get_segment()
The poorly named get_segment() function handles most of the address translation logic for hash-based MMUs. It has many ugly conditionals on whether the MMU is 32-bit or 64-bit. This patch splits the function into 32 and 64-bit versions, using the switch on mmu_type that's already in the caller (get_physical_address()) to select the right one. Most of the original function remains in mmu_helper.c to support the 6xx software loaded TLB implementations (cleaning those up is a project for another day). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
c69b6151e7
commit
0480884f14
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@ -85,8 +85,8 @@ static int pte_check_hash32(mmu_ctx_t *ctx, target_ulong pte0,
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}
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/* PTE table lookup */
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int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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int rw, int type, int target_page_bits)
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static int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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int rw, int type, int target_page_bits)
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{
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hwaddr pteg_off;
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target_ulong pte0, pte1;
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@ -157,3 +157,148 @@ int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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}
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return ret;
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}
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int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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hwaddr hash;
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target_ulong vsid;
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int ds, pr, target_page_bits;
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int ret, ret2;
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target_ulong sr, pgidx;
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pr = msr_pr;
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ctx->eaddr = eaddr;
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sr = env->sr[eaddr >> 28];
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ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
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((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
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ds = sr & 0x80000000 ? 1 : 0;
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ctx->nx = sr & 0x10000000 ? 1 : 0;
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vsid = sr & 0x00FFFFFF;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
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(int)msr_dr, pr != 0 ? 1 : 0, rw, type);
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
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hash = vsid ^ pgidx;
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
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ctx->key, ds, ctx->nx, vsid);
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ret = -1;
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if (!ds) {
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || ctx->nx == 0) {
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->hash[0] = hash;
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ctx->hash[1] = ~hash;
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/* Initialize real address with an invalid value */
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ctx->raddr = (hwaddr)-1ULL;
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ctx->ptem,
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ctx->hash[0]);
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/* Primary table lookup */
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ret = find_pte32(env, ctx, 0, rw, type, target_page_bits);
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if (ret < 0) {
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/* Secondary table lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
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ret2 = find_pte32(env, ctx, 1, rw, type,
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target_page_bits);
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if (ret2 != -1) {
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ret = ret2;
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}
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}
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#if defined(DUMP_PAGE_TABLES)
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if (qemu_log_enabled()) {
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hwaddr curaddr;
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uint32_t a0, a1, a2, a3;
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qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
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"\n", sdr, mask + 0x80);
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for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
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curaddr += 16) {
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a0 = ldl_phys(curaddr);
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a1 = ldl_phys(curaddr + 4);
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a2 = ldl_phys(curaddr + 8);
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a3 = ldl_phys(curaddr + 12);
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if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
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qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
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curaddr, a0, a1, a2, a3);
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}
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}
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}
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#endif
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} else {
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LOG_MMU("No access allowed\n");
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ret = -3;
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}
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} else {
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target_ulong sr;
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LOG_MMU("direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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/* Direct-store implies a 32-bit MMU.
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* Check the Segment Register's bus unit ID (BUID).
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*/
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sr = env->sr[eaddr >> 28];
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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switch (type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_CODE:
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/* No code fetch is allowed in direct-store areas */
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return -4;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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return -4;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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return -4;
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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ctx->raddr = eaddr;
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return 0;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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return -4;
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default:
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qemu_log("ERROR: instruction should not need "
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"address translation\n");
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return -4;
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}
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if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
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ctx->raddr = eaddr;
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ret = 2;
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} else {
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ret = -2;
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}
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}
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return ret;
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}
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@ -4,8 +4,8 @@
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#ifndef CONFIG_USER_ONLY
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int pte32_is_valid(target_ulong pte0);
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int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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int rw, int type, int target_page_bits);
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int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type);
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#endif /* CONFIG_USER_ONLY */
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@ -44,7 +44,7 @@
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* SLB handling
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*/
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ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
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static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
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{
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uint64_t esid_256M, esid_1T;
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int n;
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@ -276,8 +276,8 @@ static int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
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}
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/* PTE table lookup */
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int find_pte64(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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int rw, int type, int target_page_bits)
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static int find_pte64(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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int rw, int type, int target_page_bits)
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{
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hwaddr pteg_off;
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target_ulong pte0, pte1;
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@ -349,3 +349,89 @@ int find_pte64(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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}
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return ret;
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}
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int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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hwaddr hash;
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target_ulong vsid;
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int pr, target_page_bits;
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int ret, ret2;
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pr = msr_pr;
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ctx->eaddr = eaddr;
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ppc_slb_t *slb;
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target_ulong pageaddr;
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int segment_bits;
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LOG_MMU("Check SLBs\n");
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slb = slb_lookup(env, eaddr);
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if (!slb) {
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return -5;
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}
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if (slb->vsid & SLB_VSID_B) {
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
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segment_bits = 40;
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} else {
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
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segment_bits = 28;
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}
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target_page_bits = (slb->vsid & SLB_VSID_L)
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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ctx->nx = !!(slb->vsid & SLB_VSID_N);
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pageaddr = eaddr & ((1ULL << segment_bits)
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- (1ULL << target_page_bits));
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if (slb->vsid & SLB_VSID_B) {
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hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
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} else {
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hash = vsid ^ (pageaddr >> target_page_bits);
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}
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/* Only 5 bits of the page index are used in the AVPN */
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ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
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((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
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LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
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ctx->key, ctx->nx, vsid);
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ret = -1;
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || ctx->nx == 0) {
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->hash[0] = hash;
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ctx->hash[1] = ~hash;
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/* Initialize real address with an invalid value */
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ctx->raddr = (hwaddr)-1ULL;
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ctx->ptem,
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ctx->hash[0]);
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/* Primary table lookup */
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ret = find_pte64(env, ctx, 0, rw, type, target_page_bits);
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if (ret < 0) {
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/* Secondary table lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
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ret2 = find_pte64(env, ctx, 1, rw, type, target_page_bits);
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if (ret2 != -1) {
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ret = ret2;
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}
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}
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} else {
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LOG_MMU("No access allowed\n");
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ret = -3;
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}
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return ret;
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}
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@ -4,11 +4,10 @@
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#ifndef CONFIG_USER_ONLY
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#ifdef TARGET_PPC64
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ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr);
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void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
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int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
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int find_pte64(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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int rw, int type, int target_page_bits);
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int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type);
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#endif
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#endif /* CONFIG_USER_ONLY */
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@ -507,87 +507,35 @@ hwaddr get_pteg_offset(CPUPPCState *env, hwaddr hash, int pte_size)
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return (hash * pte_size * 8) & env->htab_mask;
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}
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static inline int find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int h, int rw,
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int type, int target_page_bits)
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{
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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return find_pte64(env, ctx, h, rw, type, target_page_bits);
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}
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#endif
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return find_pte32(env, ctx, h, rw, type, target_page_bits);
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}
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/* Perform segment based translation */
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static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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hwaddr hash;
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target_ulong vsid;
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int ds, pr, target_page_bits;
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int ret, ret2;
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int ret;
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target_ulong sr, pgidx;
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pr = msr_pr;
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ctx->eaddr = eaddr;
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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ppc_slb_t *slb;
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target_ulong pageaddr;
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int segment_bits;
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LOG_MMU("Check SLBs\n");
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slb = slb_lookup(env, eaddr);
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if (!slb) {
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return -5;
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}
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sr = env->sr[eaddr >> 28];
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ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
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((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
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ds = sr & 0x80000000 ? 1 : 0;
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ctx->nx = sr & 0x10000000 ? 1 : 0;
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vsid = sr & 0x00FFFFFF;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
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(int)msr_dr, pr != 0 ? 1 : 0, rw, type);
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
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hash = vsid ^ pgidx;
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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if (slb->vsid & SLB_VSID_B) {
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
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segment_bits = 40;
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} else {
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
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segment_bits = 28;
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}
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target_page_bits = (slb->vsid & SLB_VSID_L)
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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ds = 0;
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ctx->nx = !!(slb->vsid & SLB_VSID_N);
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pageaddr = eaddr & ((1ULL << segment_bits)
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- (1ULL << target_page_bits));
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if (slb->vsid & SLB_VSID_B) {
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hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
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} else {
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hash = vsid ^ (pageaddr >> target_page_bits);
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}
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/* Only 5 bits of the page index are used in the AVPN */
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ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
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((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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target_ulong sr, pgidx;
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sr = env->sr[eaddr >> 28];
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ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
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((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
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ds = sr & 0x80000000 ? 1 : 0;
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ctx->nx = sr & 0x10000000 ? 1 : 0;
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vsid = sr & 0x00FFFFFF;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
|
||||
(int)msr_dr, pr != 0 ? 1 : 0, rw, type);
|
||||
pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
|
||||
hash = vsid ^ pgidx;
|
||||
ctx->ptem = (vsid << 7) | (pgidx >> 10);
|
||||
}
|
||||
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
|
||||
ctx->key, ds, ctx->nx, vsid);
|
||||
ret = -1;
|
||||
|
|
@ -603,31 +551,8 @@ static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
|
|||
|
||||
/* Initialize real address with an invalid value */
|
||||
ctx->raddr = (hwaddr)-1ULL;
|
||||
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
||||
env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
|
||||
/* Software TLB search */
|
||||
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
|
||||
} else {
|
||||
LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
|
||||
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
|
||||
" hash=" TARGET_FMT_plx "\n",
|
||||
env->htab_base, env->htab_mask, vsid, ctx->ptem,
|
||||
ctx->hash[0]);
|
||||
/* Primary table lookup */
|
||||
ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
|
||||
if (ret < 0) {
|
||||
/* Secondary table lookup */
|
||||
LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
|
||||
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
|
||||
" hash=" TARGET_FMT_plx "\n", env->htab_base,
|
||||
env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
|
||||
ret2 = find_pte(env, ctx, 1, rw, type,
|
||||
target_page_bits);
|
||||
if (ret2 != -1) {
|
||||
ret = ret2;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Software TLB search */
|
||||
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
|
||||
#if defined(DUMP_PAGE_TABLES)
|
||||
if (qemu_log_enabled()) {
|
||||
hwaddr curaddr;
|
||||
|
|
@ -1415,22 +1340,36 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
|
|||
switch (env->mmu_model) {
|
||||
case POWERPC_MMU_32B:
|
||||
case POWERPC_MMU_601:
|
||||
/* Try to find a BAT */
|
||||
if (env->nb_BATs != 0) {
|
||||
ret = get_bat(env, ctx, eaddr, rw, access_type);
|
||||
}
|
||||
if (ret < 0) {
|
||||
/* We didn't match any BAT entry or don't have BATs */
|
||||
ret = get_segment32(env, ctx, eaddr, rw, access_type);
|
||||
}
|
||||
break;
|
||||
|
||||
case POWERPC_MMU_SOFT_6xx:
|
||||
case POWERPC_MMU_SOFT_74xx:
|
||||
/* Try to find a BAT */
|
||||
if (env->nb_BATs != 0) {
|
||||
ret = get_bat(env, ctx, eaddr, rw, access_type);
|
||||
}
|
||||
if (ret < 0) {
|
||||
/* We didn't match any BAT entry or don't have BATs */
|
||||
ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, access_type);
|
||||
}
|
||||
break;
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
case POWERPC_MMU_64B:
|
||||
case POWERPC_MMU_2_06:
|
||||
case POWERPC_MMU_2_06d:
|
||||
#endif
|
||||
if (ret < 0) {
|
||||
/* We didn't match any BAT entry or don't have BATs */
|
||||
ret = get_segment(env, ctx, eaddr, rw, access_type);
|
||||
}
|
||||
ret = get_segment64(env, ctx, eaddr, rw, access_type);
|
||||
break;
|
||||
#endif
|
||||
|
||||
case POWERPC_MMU_SOFT_4xx:
|
||||
case POWERPC_MMU_SOFT_4xx_Z:
|
||||
ret = mmu40x_get_physical_address(env, ctx, eaddr,
|
||||
|
|
|
|||
Loading…
Reference in New Issue