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target/riscv/cpu: Move Floating-Point fields closer

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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221217172907.8364-7-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2022-12-17 18:06:21 +01:00
parent a1a65aade6
commit 04bc302758
1 changed files with 3 additions and 3 deletions
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6
target/riscv/cpu.h
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@ -148,7 +148,6 @@ typedef struct PMUCTRState {
struct CPUArchState {
target_ulong gpr[32];
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
uint64_t fpr[32]; /* assume both F and D extensions */
/* vector coprocessor state. */
uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
@ -163,7 +162,10 @@ struct CPUArchState {
target_ulong load_res;
target_ulong load_val;
/* Floating-Point state */
uint64_t fpr[32]; /* assume both F and D extensions */
target_ulong frm;
float_status fp_status;
target_ulong badaddr;
target_ulong bins;
@ -379,8 +381,6 @@ struct CPUArchState {
target_ulong cur_pmmask;
target_ulong cur_pmbase;
float_status fp_status;
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */