target/riscv/cpu: Move Floating-Point fields closer
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221217172907.8364-7-philmd@linaro.org>
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@ -148,7 +148,6 @@ typedef struct PMUCTRState {
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struct CPUArchState {
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target_ulong gpr[32];
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target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
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uint64_t fpr[32]; /* assume both F and D extensions */
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/* vector coprocessor state. */
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uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
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@ -163,7 +162,10 @@ struct CPUArchState {
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target_ulong load_res;
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target_ulong load_val;
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/* Floating-Point state */
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uint64_t fpr[32]; /* assume both F and D extensions */
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target_ulong frm;
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float_status fp_status;
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target_ulong badaddr;
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target_ulong bins;
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@ -379,8 +381,6 @@ struct CPUArchState {
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target_ulong cur_pmmask;
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target_ulong cur_pmbase;
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float_status fp_status;
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/* Fields from here on are preserved across CPU reset. */
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QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
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QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
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